EP3SL50F780C4 Datasheet, PDF (128/341 Pages) Altera Corporation – Stratix III Device Handbook

1–118
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–68. EP3SL110 Row Pins Output Timing Parameters (Part 3 of 3)
I/O Standard
Clock
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
DIFFERENTIAL
1.8-V
8mA
SSTL CLASS I
GCLK t_co
GCLK
PLL ^tco
3.125
1.345
3.370
1.531
4.786 5.191 5.702 5.566 5.821 5.317 5.832 5.695 5.898 ns
1.996 2.100 2.313 2.326 2.329 2.208 2.426 2.436 2.318 ns
DIFFERENTIAL
GCLK t_co
1.8-V
10mA _GCLK
SSTL CLASS I
PLL ^tco
3.105
1.325
3.350
1.511
4.763 5.167 5.679 5.543 5.798 5.294 5.808 5.671 5.874 ns
1.973 2.076 2.290 2.303 2.306 2.185 2.402 2.412 2.294 ns
DIFFERENTIAL
GCLK t_co
1.8-V
12mA _GCLK
SSTL CLASS I
PLL ^tco
3.102
1.322
3.346
1.507
4.759 5.164 5.675 5.539 5.794 5.290 5.805 5.668 5.871 ns
1.969 2.073 2.286 2.299 2.302 2.181 2.399 2.409 2.291 ns
DIFFERENTIAL
1.8-V
8mA
SSTL CLASS II
GCLK t_co
GCLK
PLL ^tco
3.107
1.327
3.350
1.511
4.750 5.152 5.661 5.525 5.780 5.277 5.789 5.652 5.855 ns
1.960 2.061 2.272 2.285 2.288 2.168 2.383 2.393 2.275 ns
DIFFERENTIAL
GCLK t_co
1.8-V
16mA _GCLK
SSTL CLASS II
PLL ^tco
3.100
1.320
3.343
1.504
4.749 5.153 5.664 5.528 5.783 5.280 5.794 5.657 5.860 ns
1.959 2.062 2.275 2.288 2.291 2.171 2.388 2.398 2.280 ns
DIFFERENTIAL
2.5-V
8mA
SSTL CLASS I
GCLK t_co
GCLK
PLL ^tco
3.138
1.358
3.382
1.543
4.787 5.190 5.700 5.564 5.819 5.316 5.829 5.692 5.895 ns
1.997 2.099 2.311 2.324 2.327 2.207 2.423 2.433 2.315 ns
DIFFERENTIAL
GCLK t_co
2.5-V
12mA _GCLK
SSTL CLASS I
PLL ^tco
3.120
1.340
3.365
1.526
4.772 5.175 5.685 5.549 5.804 5.301 5.814 5.677 5.880 ns
1.982 2.084 2.296 2.309 2.312 2.192 2.408 2.418 2.300 ns
DIFFERENTIAL
GCLK t_co
2.5-V
16mA _GCLK
SSTL CLASS II
PLL ^tco
3.106
1.326
3.349
1.510
4.749 5.151 5.660 5.524 5.779 5.277 5.789 5.652 5.855 ns
1.959 2.060 2.271 2.284 2.287 2.168 2.383 2.393 2.275 ns
Table 1–69 and Table 1–70 list the EP3SL110 regional clock (RCLK) adder values that
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–69 lists the EP3SL110 column pin delay adders when using the regional clock.
Table 1–69. EP3SL110 Column Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
0.186
2.391
-0.374
-2.001
0.171
2.371
-0.162
-1.786
C2
V_CCL=
1.1 V
0.245
3.577
-0.226
-2.669
C3
V_CCL=
1.1 V
0.255
4.036
-0.233
-2.844
C4
C4L
I3
I4
I4L
V_CCL=
1.1 V
V_CCL=
1.1 V
V_CCL=
0.9 V
V_CCL=
1.1 V
V_CCL=
1.1 V
V_CCL=
1.1 V
V_CCL=
0.9 V
0.268 0.261 0.393 0.248 0.277 0.267 0.364
4.418 4.225 4.574 4.044 4.442 4.246 4.635
-0.244 -0.239 -0.367 -0.111 -0.123 -0.116 -0.296
-2.996 -2.879 -2.722 -2.699 -3.067 -2.798 -2.773
Units
ns
ns
ns
ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation