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EP3SL50F780C4 Datasheet, PDF (227/341 Pages) Altera Corporation – Stratix III Device Handbook
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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–217
Table 1–104. EP3SE50 Row Pins Output Timing Parameters (Part 5 of 5)
I/O
Standard
Clock
Fast Model
Industrial Commercial
C2
VCCL=
1.1 V
C3
VCCL=
1.1 V
C4
VCCL=
1.1 V
C4L
VCCL= VCCL=
1.1 V 0.9 V
I3
VCCL=
1.1 V
I4
VCCL=
1.1 V
I4L
VCCL= VCCL=
1.1 V 0.9 V
Units
GCLK tco
4mA
GCLK
PLL
tco
2.997
1.329
3.219
1.512
4.580 4.985 5.500 5.364 5.576 5.110 5.627 5.491 5.644 ns
1.926 2.014 2.217 2.236 2.155 2.128 2.334 2.352 2.143 ns
1.2-V
HSTL
CLASS I
GCLK tco
6mA
GCLK
PLL
tco
2.985
1.320
3.207
1.504
4.569 4.973 5.488 5.352 5.564 5.099 5.616 5.480 5.633 ns
1.917 2.005 2.208 2.227 2.146 2.119 2.325 2.343 2.134 ns
GCLK tco
8mA
GCLK
PLL
tco
2.982
1.319
3.205
1.504
4.573 4.978 5.494 5.358 5.570 5.105 5.623 5.487 5.640 ns
1.924 2.013 2.217 2.236 2.155 2.128 2.335 2.353 2.144 ns
GCLK tco
3.0-V PCI
—
GCLK
PLL
tco
3.116
1.414
3.340
1.598
4.634 5.027 5.530 5.394 5.578 5.156 5.661 5.525 5.651 ns
1.951 2.030 2.223 2.242 2.160 2.148 2.343 2.360 2.151 ns
3.0-V
PCI-X
GCLK tco
—
GCLK
PLL
tco
3.116
1.414
3.340
1.598
4.634 5.027 5.530 5.394 5.578 5.156 5.661 5.525 5.651 ns
1.951 2.030 2.223 2.242 2.160 2.148 2.343 2.360 2.151 ns
Table 1–115 through Table 1–108 list the maximum I/O timing parameters for
EP3SE50 devices for differential I/O standards.
Table 1–105 lists the EP3SE50 column pins input timing parameters for differential
I/O standards.
Table 1–105. EP3SE50 Column Pins Input Timing Parameters (Part 1 of 3)
I/O Standard
LVDS
MINI-LVDS
RSDS
DIFFERENTIAL
1.2-V HSTL
CLASS I
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Clock
Industrial Commercial
VCCL=
1.1 V
VCCL=
1.1 V
VCCL=
1.1 V
VCCL=
1.1 V
VCCL=
0.9 V
VCCL=
1.1 V
VCCL=
1.1 V
VCCL=
1.1 V
VCCL= Units
0.9 V
tsu
GCLK
th
GCLK tsu
PLL th
tsu
GCLK
th
GCLK tsu
PLL th
GCLK tsu
th
GCLK tsu
PLL th
tsu
GCLK
th
GCLK tsu
PLL th
-0.730
0.848
1.120
-0.867
-0.730
0.848
1.120
-0.867
-0.738
0.856
1.112
-0.859
-0.738
0.856
1.112
-0.859
-0.751
0.884
1.138
-0.870
-0.751
0.884
1.138
-0.870
-0.763
0.896
1.126
-0.858
-0.763
0.896
1.126
-0.858
-1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617 ns
1.299 1.436 1.571 1.501 1.798 1.446 1.583 1.516 1.835 ns
1.796 2.027 2.253 2.141 2.145 2.036 2.262 2.145 2.193 ns
-1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710 ns
-1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617 ns
1.299 1.436 1.571 1.501 1.798 1.446 1.583 1.516 1.835 ns
1.796 2.027 2.253 2.141 2.145 2.036 2.262 2.145 2.193 ns
-1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710 ns
-1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 ns
1.309 1.447 1.587 1.517 1.814 1.457 1.598 1.531 1.850 ns
1.786 2.016 2.237 2.125 2.129 2.025 2.247 2.130 2.178 ns
-1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 ns
-1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 ns
1.309 1.447 1.587 1.517 1.814 1.457 1.598 1.531 1.850 ns
1.786 2.016 2.237 2.125 2.129 2.025 2.247 2.130 2.178 ns
-1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2
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