EP3SL50F780C4 Datasheet, PDF (100/341 Pages) Altera Corporation – Stratix III Device Handbook

1–90
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–58 lists the EP3SL70 row pins output timing parameters for differential I/O
standards.
Table 1–58. EP3SL70 Row Pins Output Timing Parameters (Part 1 of 3)
I/O Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
LVDS
GCLK t_co
— _GCLK
PLL ^tco
2.668
3.062
2.842
3.288
3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.795 4.940 ns
4.646 5.055 5.575 5.431 5.630 5.186 5.709 5.565 5.694 ns
LVDS_E_1R
GCLK t_co
— _GCLK
PLL ^tco
3.044
2.668
3.278
2.842
4.684 5.101 5.629 5.485 5.684 5.237 5.770 5.626 5.755 ns
3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.795 4.940 ns
LVDS_E_3R
GCLK t_co
— _GCLK
PLL ^tco
3.062
3.044
3.288
3.278
4.646 5.055 5.575 5.431 5.630 5.186 5.709 5.565 5.694 ns
4.684 5.101 5.629 5.485 5.684 5.237 5.770 5.626 5.755 ns
MINI-LVDS
GCLK t_co
— _GCLK
PLL ^tco
2.668
3.062
2.842
3.288
3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.795 4.940 ns
4.646 5.055 5.575 5.431 5.630 5.186 5.709 5.565 5.694 ns
MINI-
LVDS_E_1R
GCLK t_co
— _GCLK
PLL ^tco
3.044
3.098
3.278
3.331
4.684 5.101 5.629 5.485 5.684 5.237 5.770 5.626 5.755 ns
4.730 5.145 5.672 5.528 5.727 5.280 5.809 5.665 5.794 ns
MINI-
LVDS_E_3R
GCLK t_co
— _GCLK
PLL ^tco
3.084
3.080
3.317
3.313
4.717 5.132 5.659 5.515 5.714 5.266 5.796 5.652 5.781 ns
4.715 5.132 5.660 5.516 5.715 5.266 5.798 5.654 5.783 ns
RSDS
GCLK t_co
— _GCLK
PLL ^tco
3.096
3.085
3.328
3.318
4.716 5.129 5.654 5.510 5.709 5.263 5.791 5.647 5.776 ns
4.712 5.125 5.651 5.507 5.706 5.260 5.788 5.644 5.773 ns
RSDS_E_1R
GCLK t_co
— _GCLK
PLL ^tco
3.082
3.093
3.315
3.325
4.710 5.123 5.649 5.505 5.704 5.258 5.787 5.643 5.772 ns
4.711 5.124 5.648 5.504 5.703 5.257 5.785 5.641 5.770 ns
RSDS_E_3R
GCLK t_co
— _GCLK
PLL ^tco
3.083
3.069
3.316
3.302
4.709 5.122 5.647 5.503 5.702 5.257 5.785 5.641 5.770 ns
4.694 5.107 5.633 5.489 5.688 5.242 5.770 5.626 5.755 ns
DIFFERENTIAL
1.2-V
HSTL CLASS I
4mA
GCLK t_co
GCLK
PLL ^tco
3.066
3.063
3.298
3.296
4.690 5.103 5.629 5.485 5.684 5.238 5.766 5.622 5.751 ns
4.691 5.106 5.632 5.488 5.687 5.241 5.770 5.626 5.755 ns
DIFFERENTIAL
1.2-V
HSTL CLASS I
6mA
GCLK t_co
GCLK
PLL ^tco
3.064
3.113
3.296
3.349
4.681 5.094 5.619 5.475 5.674 5.228 5.756 5.612 5.741 ns
4.752 5.167 5.695 5.551 5.750 5.302 5.832 5.688 5.817 ns
DIFFERENTIAL
1.2-V
HSTL CLASS I
8mA
GCLK t_co
GCLK
PLL ^tco
3.089
3.071
3.325
3.306
4.734 5.150 5.678 5.534 5.733 5.285 5.817 5.673 5.802 ns
4.712 5.128 5.656 5.512 5.711 5.263 5.795 5.651 5.780 ns
DIFFERENTIAL
1.5-V
HSTL CLASS I
4mA
GCLK t_co
GCLK
PLL ^tco
3.117
3.102
3.352
3.337
4.752 5.167 5.694 5.550 5.749 5.302 5.832 5.688 5.817 ns
4.738 5.152 5.679 5.535 5.734 5.287 5.817 5.673 5.802 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation