EP3SL50F780C4 Datasheet, PDF (168/341 Pages) Altera Corporation – Stratix III Device Handbook

1–158
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–83. EP3SL200 Column Pins Output Timing Parameters (Part 7 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
4mA
GCLK t_co
GCLK
PLL ^tco
3.524
3.923
3.524
3.923
5.175 5.375 5.888 5.745 6.150 5.375 5.888 5.745 6.150 ns
5.810 6.015 6.592 6.420 6.907 6.015 6.592 6.420 6.907 ns
6mA
GCLK t_co
GCLK
PLL ^tco
3.516
3.915
3.516
3.915
5.166 5.366 5.879 5.736 6.141 5.366 5.879 5.736 6.141 ns
5.801 6.006 6.583 6.411 6.898 6.006 6.583 6.411 6.898 ns
1.2-V
HSTL
CLASS I
8mA
GCLK t_co
GCLK
PLL ^tco
3.517
3.916
3.517
3.916
5.174 5.374 5.888 5.745 6.150 5.374 5.888 5.745 6.150 ns
5.809 6.014 6.592 6.420 6.907 6.014 6.592 6.420 6.907 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.506
3.905
3.506
3.905
5.161 5.361 5.874 5.731 6.136 5.361 5.874 5.731 6.136 ns
5.796 6.001 6.578 6.406 6.893 6.001 6.578 6.406 6.893 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.506
3.905
3.506
3.905
5.161 5.361 5.875 5.732 6.137 5.361 5.875 5.732 6.137 ns
5.796 6.001 6.579 6.407 6.894 6.001 6.579 6.407 6.894 ns
1.2-V
HSTL
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.527
3.926
3.527
3.926
5.177 5.376 5.888 5.745 6.150 5.376 5.888 5.745 6.150 ns
5.812 6.016 6.592 6.420 6.907 6.016 6.592 6.420 6.907 ns
3.0-V PCI
GCLK t_co 3.630
—
GCLK
PLL ^tco
4.029
3.630
4.029
5.222 5.410 5.913 5.770 6.175 5.410 5.913 5.770 6.175 ns
5.857 6.050 6.617 6.445 6.932 6.050 6.617 6.445 6.932 ns
3.0-V
PCI-X
GCLK t_co 3.630
—
GCLK
PLL ^tco
4.029
3.630
4.029
5.222 5.410 5.913 5.770 6.175 5.410 5.913 5.770 6.175 ns
5.857 6.050 6.617 6.445 6.932 6.050 6.617 6.445 6.932 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation