EP3SL50F780C4 Datasheet, PDF (223/341 Pages) Altera Corporation – Stratix III Device Handbook

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–213
Table 1–103. EP3SE50 Column Pins Output Timing Parameters (Part 6 of 6)
I/O
Standard
Clock
GCLK t_co
4mA
GCLK
PLL
t_co
GCLK t_co
6mA
GCLK
PLL
t_co
1.2-V
HSTL
CLASS I
GCLK t_co
8mA
GCLK
PLL
t_co
GCLK t_co
10mA
GCLK
PLL
t_co
GCLK t_co
12mA
GCLK
PLL
t_co
1.2-V
HSTL
CLASS II
GCLK t_co
16mA
GCLK
PLL
t_co
3.0-V PCI
GCLK t_co
—
GCLK
PLL
t_co
3.0-V
PCI-X
GCLK t_co
—
GCLK
PLL
t_co
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
3.048
3.058 4.317 4.683 5.208 5.088 5.302 4.683 5.208 5.088 5.302 ns
3.397
3.371 4.777 5.212 5.710 5.565 5.864 5.212 5.710 5.565 5.864 ns
3.040
3.050 4.308 4.668 5.191 5.071 5.290 4.668 5.191 5.071 5.290 ns
3.389
3.363 4.768 5.203 5.701 5.556 5.855 5.203 5.701 5.556 5.855 ns
3.041
3.051 4.315 4.674 5.187 5.067 5.293 4.674 5.187 5.067 5.293 ns
3.390
3.364 4.775 5.212 5.710 5.565 5.864 5.212 5.710 5.565 5.864 ns
3.030
3.040 4.302 4.661 5.164 5.044 5.287 4.661 5.164 5.044 5.287 ns
3.379
3.353 4.762 5.198 5.696 5.551 5.850 5.198 5.696 5.551 5.850 ns
3.030
3.040 4.302 4.661 5.165 5.045 5.279 4.661 5.165 5.045 5.279 ns
3.379
3.353 4.762 5.198 5.697 5.552 5.851 5.198 5.697 5.552 5.851 ns
3.061
3.061 4.318 4.685 5.243 5.123 5.316 4.685 5.243 5.123 5.316 ns
3.400
3.374 4.778 5.213 5.710 5.565 5.864 5.213 5.710 5.565 5.864 ns
3.154
3.164 4.363 4.710 5.218 5.098 5.347 4.710 5.218 5.098 5.347 ns
3.503
3.477 4.823 5.247 5.735 5.590 5.889 5.247 5.735 5.590 5.889 ns
3.154
3.164 4.363 4.710 5.218 5.098 5.347 4.710 5.218 5.098 5.347 ns
3.503
3.477 4.823 5.247 5.735 5.590 5.889 5.247 5.735 5.590 5.889 ns
Table 1–104 lists the EP3SE50 row pins output timing parameters for single-ended
I/O standards.
Table 1–104. EP3SE50 Row Pins Output Timing Parameters (Part 1 of 5)
I/O
Standard
Clock
3.3-V
LVTTL
4mA
GCLK t_co
GCLK
PLL
t_co
8mA
GCLK t_co
GCLK
PLL
t_co
GCLK t_co
12mA
GCLK
PLL
t_co
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
3.161
3.395 4.722 5.117 5.622 5.486 5.755 5.247 5.754 5.618 5.832 ns
1.488
1.692 2.101 2.185 2.381 2.400 2.349 2.304 2.505 2.523 2.344 ns
3.095
3.324 4.612 5.005 5.508 5.372 5.611 5.134 5.638 5.502 5.683 ns
1.395
1.587 1.971 2.047 2.237 2.256 2.205 2.163 2.356 2.374 2.195 ns
3.016
3.235 4.506 4.905 5.412 5.276 5.483 5.035 5.539 5.403 5.551 ns
1.314
1.493 1.852 1.924 2.109 2.128 2.077 2.036 2.224 2.242 2.063 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2