EP3SL50F780C4 Datasheet, PDF (212/341 Pages) Altera Corporation – Stratix III Device Handbook

1–202
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–99 and Table 1–100 list the EP3SL340 regional (RCLK) clock adder values that
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–99 lists the EP3SL340 column pin delay adders when using the regional clock.
Table 1–99. EP3SL340 Column Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
0.318
2.716
-0.341
-2.36
0.171
2.739
-0.107
-2.128
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
0.255 0.247 0.257 0.244 0.369 0.37 0.253 0.232 0.336 ns
4.379 4.508 4.926 4.717 5.376 4.508 4.94 4.89 5.434 ns
-0.18 -0.169 -0.171 -0.167 -0.362 -0.03 -0.043 -0.034 -0.287 ns
-3.344 -3.384 -3.571 -3.487 -3.545 -3.246 -3.636 -3.357 -3.544 ns
Table 1–100 lists the EP3SL340 row pin delay adders when using the regional clock.
Table 1–100. EP3SL340 Row Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
0.075
0.157
-0.052
-0.157
0.079
0.151
-0.066
-0.139
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
0.133 0.124 0.125 0.124 0.307 0.117 0.116 0.117 0.31 ns
0.262 0.274 0.306 0.288 0.464 0.268 0.291 0.278 0.46 ns
-0.107 -0.098 -0.127 -0.129 -0.282 -0.082 -0.118 -0.085 -0.285 ns
-0.232 -0.248 -0.272 -0.259 -0.422 -0.252 -0.256 -0.244 -0.444 ns
EP3SE50 I/O Timing Parameters
Table 1–101 through Table 1–104 list the maximum I/O timing parameters for
EP3SE50 devices for single-ended I/O standards.
Table 1–101 lists the EP3SE50 column pins input timing parameters for single-ended
I/O standards.
Table 1–101. EP3SE50 Column Pins Input Timing Parameters (Part 1 of 4)
I/O
Standard
Clock
GCLK ^tsu
t_h
3.3-V LVTTL
GCLK ^tsu
PLL _th
3.3-V
LVCMOS
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
-0.743
-0.742 -1.063 -1.165 -1.374 -1.329 -1.605 -1.165 -1.374 -1.329 -1.605 ns
0.870
0.869 1.241 1.366 1.595 1.538 1.815 1.366 1.595 1.538 1.815 ns
-1.037
-1.037 -1.466 -1.593 -1.830 -1.772 -2.038 -1.593 -1.830 -1.772 -2.038 ns
1.290
1.290 1.836 2.009 2.292 2.207 2.484 2.009 2.292 2.207 2.484 ns
-0.743
-0.742 -1.063 -1.165 -1.374 -1.329 -1.605 -1.165 -1.374 -1.329 -1.605 ns
0.870
0.869 1.241 1.366 1.595 1.538 1.815 1.366 1.595 1.538 1.815 ns
-1.037
-1.037 -1.466 -1.593 -1.830 -1.772 -2.038 -1.593 -1.830 -1.772 -2.038 ns
1.290
1.290 1.836 2.009 2.292 2.207 2.484 2.009 2.292 2.207 2.484 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation