EP3SL50F780C4 Datasheet, PDF (310/341 Pages) Altera Corporation – Stratix III Device Handbook

1–300
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–135. EP3SE260 Column Pins Input Timing Parameters (Part 3 of 3)
I/O Standard Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
t_su
DIFFERENTIAL ^GCLK
2.5-V SSTL
t_h
CLASS I
GCLK ^tsu
PLL _th
DIFFERENTIAL
2.5-V SSTL
GCLK
t_su
t_h
CLASS II
GCLK ^tsu
PLL _th
-1.153
1.289
1.103
-0.824
-1.161
1.297
1.095
-0.816
-1.221
1.376
1.122
-0.821
-1.233
1.388
1.110
-0.809
-1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 ns
2.114 2.150 2.330 2.237 2.711 2.177 2.355 2.237 2.711 ns
1.882 1.986 2.207 2.099 2.096 1.998 2.217 2.099 2.096 ns
-1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 ns
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 ns
2.124 2.161 2.346 2.253 2.727 2.188 2.370 2.253 2.727 ns
1.872 1.975 2.191 2.083 2.080 1.987 2.202 2.083 2.080 ns
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 ns
Table 1–136 lists the EP3SE260 row pins input timing parameters for differential I/O
standards.
Table 1–136. EP3SE260 Row Pins Input Timing Parameters (Part 1 of 3)
I/O Standard
LVDS
MINI-LVDS
RSDS
DIFFERENTIAL
1.2-V
HSTL CLASS I
DIFFERENTIAL
1.2-V
HSTL CLASS II
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
-1.332
1.476
0.869
-0.581
-1.332
1.476
0.869
-0.581
-1.332
1.476
0.869
-0.581
-1.137
1.274
1.064
-0.783
-1.137
1.274
1.064
-0.783
-1.401
1.563
0.886
-0.578
-1.401
1.563
0.886
-0.578
-1.401
1.563
0.886
-0.578
-1.216
1.369
1.071
-0.772
-1.216
1.369
1.071
-0.772
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 ns
1.994 1.939 2.157 2.071 2.526 1.934 2.145 2.071 2.526 ns
1.991 2.205 2.405 2.282 2.297 2.252 2.458 2.282 2.297 ns
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 ns
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 ns
1.994 1.939 2.157 2.071 2.526 1.934 2.145 2.071 2.526 ns
1.991 2.205 2.405 2.282 2.297 2.252 2.458 2.282 2.297 ns
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 ns
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 ns
1.994 1.939 2.157 2.071 2.526 1.934 2.145 2.071 2.526 ns
1.991 2.205 2.405 2.282 2.297 2.252 2.458 2.282 2.297 ns
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 ns
-1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400 ns
2.088 2.122 2.297 2.206 2.656 2.156 2.330 2.206 2.656 ns
1.866 1.981 2.216 2.098 2.118 1.985 2.221 2.098 2.118 ns
-1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581 ns
-1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400 ns
2.088 2.122 2.297 2.206 2.656 2.156 2.330 2.206 2.656 ns
1.866 1.981 2.216 2.098 2.118 1.985 2.221 2.098 2.118 ns
-1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation