AK4492ECB Datasheet, PDF (94/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
10. Recommended External Circuits
ACPU
0.1F
0.1F
51ohm
0.1F
DVSS
0V
DVDD
1F ^1.8V
AK4492
BICK/BCK/DCLK(J1)
SDATA/DINL/DSDL(H1)
LRCK/DINR/DSDR(G1)
SMUTE/CSN(F1)
SLOW/CDTI/SDA(E1)
DIF0/DZFL(D1)
DIF1/DZFR(C1)
DEM0/DSDL(B1)
DVSS(K2)
TVDD(J2)
PDN(H2)
SSLOW/WCK(G2)
TDMO(F2)
SD/CCLK/SCL(E2)
DIF2/CAD0(D2)
HLOAD/I2C(C2)
GAIN/DSDR(B2)
ACKS/CAD1(A2)
DVDD(K3)
MCLK(J3)
LDOE(H3)
PSN(D3)
TDM1(B3)
TDM0/DCLK(A3)
AVDD(K4)
AVSS(J4)
DCHAIN(B4)
INVR(A4)
TESTE(B5)
VREFHR(A5,A6)
VREFLR(A7,A8)
VCMR(B8)
External
Regulator
Circuit
1F
AOUTRN(A9)
AOUTRP(B9)
VDDR(C9,C10,D9)
VSSR(D10,E9,E10)
1F
External
LPF
Circuit
VSSL(F9,F10,G10)
VDDL(G9,H9,H10)
AOUTLP(J9)
AOUTLN(K9)
1F
External
LPF
Circuit
VCML(J8)
VREFLL(L7,K8)
VREFHL(K5,K6)
1F
External
Regulator
Circuit
EXTR(J5)
33kohm
VSS
0V
DVSS VSS
Power Supply
6V
AOUTR
AOUTL
VDD
5V
Figure 72. Typical Connection Diagram
(AVDD = TVDD = DVDD = 1.8 V, VDDL/R = 5.0 V, LDOE pin = “L”, Register control mode)
Note:
- Chip Address = “00”. BICK = 64fs, LRCK = fs
- Power lines of AVDD, TVDD, VDDL and VDDR should be distributed separately from the point
with low impedance of regulator etc.
- AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane. (Analog
ground should has low impedance as a solid pattern. THD+N characteristics will degrade if
there are impedances between each VSS.)
- It is recommended to input MCLK via a dumping resistor of 51ohm. Without the resistor, there is a
possibilrty that THD+N characteristic degrades because of high-frequency noise of MCLK.
- All input pins except pull-down/pull-up pins should not be allowed to float.
016011073-E-00
- 94 -
2016/12