AK4492ECB Datasheet, PDF (30/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
Parameter
Symbol Min. Typ. Max.
Control Interface Timing (3-wire IF mode):
CCLK Period
tCCK 200 -
-
CCLK Pulse Width Low
CCLK Pulse Width High
CDTI Setup Time
tCCKL
80
-
-
tCCKH 80
-
-
tCDS
40
-
-
CDTI Hold Time
CSN “H” Time
CSN “” to CCLK “”
CCLK “” to CSN “”
Control Interface Timing (I²C Bus mode):
tCDH
40
-
-
tCSW 150 -
-
tCSS
50
-
-
tCSH
50
-
-
SCL Clock Frequency
fSCL
-
- 400
Bus Free Time Between Transmissions
tBUF
1.3
-
-
Start Condition Hold Time (prior to first clock pulse)
tHD:STA 0.6
-
-
Clock Low Time
tLOW
1.3
-
-
Clock High Time
tHIGH 0.6 -
-
Setup Time for Repeated Start Condition
tSU:STA 0.6 -
-
SDA Hold Time from SCL Falling
(Note 44) tHD:DAT 0
-
-
SDA Setup Time from SCL Rising
tSU:DAT 0.1 -
-
Rise Time of Both SDA and SCL Lines
tR
-
- 0.3
Fall Time of Both SDA and SCL Lines
tF
-
- 0.3
Setup Time for Stop Condition
tSU:STO 0.6 -
-
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
-
50
Capacitive load on bus
Cb
-
- 400
Power-down & Reset Timing
(Note 45)
PDN Accept Pulse Width
tAPD 150 -
-
PDN Reject Pulse Width
tRPD
-
-
30
Note 44. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 45. The AK4492 should be reset by bringing the PDN pin “L” upon power-up.
Note 46. I²C -bus is a trademark of NXP B.V.
Unit
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
kHz
usec
usec
usec
usec
usec
usec
usec
usec
usec
usec
nsec
pF
nsec
nsec
016011073-E-00
- 30 -
2016/12