AK4492ECB Datasheet, PDF (74/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
■ Power-OFF/Reset Function
Power-off and Reset function of the AK4492 are controlled by PW bit, RSTN bit and MCLK (Table 42).
Mode
PDN
Pin
Power Down _L
MCLK Stop
H
Power OFF
H
Reset
H
Normal
Operation
H
(- : Do not care)
Table 42. Power Off, Reset Function
MCLK
Supply
PW bit
RSTN
bit
DIGITAL ANALOG
Block
Block
－
－
－
OFF
OFF
No
－
－
OFF
OFF
Yes
0
－
OFF
OFF
Yes
1
0
OFF
ON
Yes
1
1
ON
ON
LDO
Register
OFF
ON
ON
ON
ON
Analog
Output
Hi-Z
Hi-Z
Hi-Z
VCML/R
Signal output
[1] Power ON/OFF by MCLK Clock
The AK4492 detects a clock stop and all circuits including MCLK stop detection circuit, control register
and IREF (except LDO when the LDOE pin = “H”) stop operation if MCLK is not input for 1us (min.) during
operation (PDN pin = “H”). In this case, the analog output goes floating state (Hi-Z). The AK4492 returns
to normal operation if PW bit and RSTN bit are “1” after starting to supply MCLK again. The zero detect
function is disabled when MCLK is stopped.
PDN pin
(4)
Internal
State
Normal Operation
Power-off
Normal Operation
Clock In
MCLK,
MCLK Stop
D/A In
(Digital)
D/A Out
(Analog)
(3)
(1)
(1)
(5)
(2) Hi-Z
Figure 57. Power ON/OFF by MCLK Clock
Notes:
(1) The AK4492 detects MCLK stop and becomes power off state when MCLK edge is not detected for
1us (min.) during operation.
(2) The analog output goes to floating state (Hi-Z).
(3) Click noise can be reduced by inputting “0” data when stopping and resuming MCLK supply.
(4) Resume MCLK input to release the power-off state by MCLK. In this case, power-up sequence by
the PDN pin or power-on sequence by PW bit is not necessary.
(5) The analog output corresponding to the digital input has group delay (GD).
016011073-E-00
- 74 -
2016/12