AK4492ECB Datasheet, PDF (8/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
No.
Pin
Name
I/O
Protection
Diode
Function
SLOW I
Digital Filter Select Pin in Pin Control Mode (PSN pin = “H”)
E1 CDTI
I
－
/DVSS
Control Data Input Pin in Register Control Mode
(PSN pin = “L”, I2C pin = “L”)
SDA I/O
Control Data Input Pin (PSN pin = “L”, I2C pin = “H”)
SD
I
Digital Filter Select Pin in Pin Control Mode (PSN pin = “H”)
E2 CCLK
I
－
/DVSS
Control Data Clock Pin in Register Control Mode
(PSN pin = “L”, I2C pin = “L”)
SCL I
Control Data Clock Input Pin (PSN pin = “L”, I2C pin = “H”)
E9 VSSR -
-
Analog Ground Pin
E10 VSSR -
-
Analog Ground Pin
Soft Mute Pin in Pin Control Mode (PSN pin = “H”)
SMUTE I
When this pin is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
F1
TVDD/DVSS Chip Select Pin in Register Control Mode
CSN I
(PSN pin = “L”, I2C pin = “L”)
This Pin should be connected to DVSS
(PSN pin = “L”, I2C pin = “H”)
F2
TDMO
O
TVDD/DVSS
Audio Data Onput in Daisy Chain Mode
(Internal pull-down pin)
F9 VSSL -
-
Analog Ground Pin
F10 VSSL -
-
Analog Ground Pin
LRCK I
L/R Clock Pin in PCM Mode
G1 DINR I TVDD/DVSS Rch Audio Data Input Pin in EXDF Mode
DSDR I
DSD Rch Data Input Pin in DSD Mode (DSDPATH bit = “1”)
G2
SSLOW
WCK
I
I
TVDD/DVSS
Digital Filter Select Pin in Pin Control Mode (PSN pin= “H”)
Word Clock input Pin in EXDF Mode (PSN pin = “L”)
G9 VDDL -
-
Lch Analog Power Supply Pin
G10 VSSL -
-
Analog Ground Pin
SDATA I
Audio Data Input Pin in PCM Mode
H1 DINL I TVDD/DVSS Lch Audio Data Input Pin in EXDF Mode
DSDL I
DSD Lch Data Input Pin in DSD Mode (DSDPATH bit = “1”)
Power-Up, Power-Down Pin
H2 PDN I TVDD/DVSS When at “L”, the AK4492 is in power-down mode and is held in
reset.The AK4492 must always be reset upon power-up.
H3 LDOE I TVDD/DVSS Internal LDO Enable Pin. “L”: Disable, “H”: Enable
H9 VDDL -
-
Lch Analog Power Supply Pin
H10 VDDL -
-
Lch Analog Power Supply Pin
BICK I
Audio Data Clock Pin in PCM Mode
J1 BCK I TVDD/DVSS Audio Data Clock Pin in EXDF Mode
DCLK I
DSD Clock Pin in DSD Mode (DSDPATH bit = “1”)
J2 TVDD -
-
Digital Power Supply Pin.
LDOE pin = “L”: (DVDD) ~ 3.6 V / LDOE pin = “H”: 3.0 ~ 3.6V
J3 MCLK I AVDD/AVSS Master Clock Input Pin
J4 AVSS -
-
Analog Ground Pin
J5
EXTR
I
VDDL/VSSL
External Resistor Connect Pin
Rext=33 kΩ(±1 %, Note 1) toAVSS
Left channel Common Voltage Pin,
J8 VCML - VDDL/VSSL Normally connected to VREFLL with a 1 uF electrolytic cap. This
pin is inhibited to connect other devices.
J9 AOUTLP O VDDL/VSSL Lch Positive Analog Output Pin
016011073-E-00
-8-
2016/12