AK4492ECB Datasheet, PDF (26/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
■ Switching Characteristics
(Ta = -40 ~ 85 C; VDDL/R = 4.755.25 V, AVDD = TVDD = 1.73.6V, DVDD = 1.7~1.98 V, C_L = 20 pF)
Parameter
Symbol Min.
Typ.
Max. Unit
Master Clock Timing
Frequency
Duty Cycle
Minimum Pulse Width
fCLK
dCLK
tCLKH
tCLKL
2.048
40
9.155
9.155
-
49.152 MHz
-
60
%
-
-
nsec
-
-
nsec
LRCK Clock Timing (Note 37)
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
Duty Cycle
fsn
8
-
54
kHz
fsd
54
-
108
kHz
fsq
108
-
216
kHz
fso
-
384
-
kHz
fsh
-
768
-
kHz
Duty
45
-
55
%
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High time
Low time
fsn
8
-
fsd
54
-
fsq
108
-
tLRH 1/128fs
-
tLRL 1/128fs
-
54
kHz
108
kHz
216
kHz
-
nsec
-
nsec
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
Double Speed Mode
High time
Low time
fsn
8
-
fsd
54
-
tLRH 1/256fs
-
tLRL 1/256fs
-
54
kHz
108
kHz
-
nsec
-
nsec
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
High time
Low time
fsn
8
-
tLRH 1/512fs
-
tLRL 1/512fs
-
54
kHz
-
nsec
-
nsec
Note 37. The MCLK frequency must be changed while the AK4492 is in reset state by setting the PDN pin
= “L” or RSTN bit = “0”.
016011073-E-00
- 26 -
2016/12