AK4492ECB Datasheet, PDF (28/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
Parameter
Symbol Min.
Typ.
PCM Audio Interface Timing
Normal Mode (TDM[1:0] bits = “00”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
BICK Pulse Width Low
BICK Pulse Width High
tBCK 1/256fsn
-
tBCK 1/128fsd
-
tBCK 1/64fsq
-
tBCK 1/64fso
-
tBCK 1/64fsh
-
tBCKL
9
-
tBCKH
9
-
BICK “” to LRCK Edge
(Note 39) tBLR
5
-
LRCK Edge to BICK “”
(Note 39) tLRB
5
-
SDATA Hold Time
tSDH
5
-
SDATA Setup Time
tSDS
5
-
TDM128 mode (TDM[1:0] bits = “01”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
tBCK 1/128fsn
-
tBCK 1/128fsd
-
tBCK 1/128fsq
-
tBCKL
14
-
tBCKH
14
-
BICK “” to LRCK Edge
(Note 39) tBLR
14
-
LRCK Edge to BICK “”
(Note 39) tLRB
14
-
SDATA Hold Time
tSDH
5
-
SDATA Setup Time
tSDS
5
-
TDM256 mode (TDM[1:0] bits = “10”)
BICK Period
Normal Speed Mode
tBCK 1/256fsn
-
Double Speed Mode
(Note 40) _{tBCK 1/256fsd}
-
BICK Pulse Width Low
tBCKL
14
-
BICK Pulse Width High
tBCKH
14
-
BICK “” to LRCK Edge
(Note 39) tBLR
14
-
LRCK Edge to BICK “”
(Note 39) tLRB
14
-
TDMO Setup time BICK “”
tBSS
5
-
TDMO Hold time BICK “” (Note 42) ^tBSH
5
-
SDATA Hold Time
tSDH
5
-
SDATA Setup Time
tSDS
5
-
TDM512 mode (TDM[1:0] bits = “11”)
BICK Period
-
Normal Speed Mode
(Note 41) _{tBCK 1/512fsn}
-
BICK Pulse Width Low
tBCKL
14
-
BICK Pulse Width High
tBCKH
14
-
BICK “” to LRCK Edge
(Note 39) tBLR
14
-
LRCK Edge to BICK “”
(Note 39) tLRB
14
-
TDMO Setup time BICK “”
tBSS
5
-
TDMO Hold time BICK “” (Note 42) ^tBSH
5
-
SDATA Hold Time
tSDH
5
-
SDATA Setup Time
tSDS
5
-
Note 39. BICK rising edge must not occur at the same time as LRCK edge.
Note 40. Daisy Chain Mode, fsd (max) = 96 kHz if “TVDD < 3.0V”.
Note 41. Daisy Chain Mode, fsn (max) = 48 kHz if “TVDD < 3.0V”.
Note 42. LDOE pin = “L”, tBSH (min) = 4 nsec if “TVDD > 2.6V”.
Max.
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016011073-E-00
- 28 -
2016/12