AK4492ECB Datasheet, PDF (27/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
(Ta = -40 ~ 85 C; VDDL/R = 4.755.25 V, TVDD = AVDD = (DVDD)  3.6V, DVDD = 1.7~1.98 V,
C_L = 20 pF, PSN pin = “L”, AFSD bit = “1”)
Parameter
Symbol Min.
Typ.
Max. Unit
Master Clock Timing (FS Auto Detect Mode)
Frequency
Duty Cycle
Minimum Pulse Width
fCLK
dCLK
tCLKH
tCLKL
7.68
40
9.155
9.155
-
49.152 MHz
-
60
%
-
-
nsec
-
-
nsec
LRCK Clock Timing (FS Auto Detect Mode) (Note 38)
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
Duty Cycle
fsn
30
-
fsd
88.2
-
fsq
176.4
-
fso
-
384
fsh
-
768
Duty
45
-
54
kHz
108
kHz
216
kHz
-
kHz
-
kHz
55
%
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High time
Low time
fsn
30
-
fsd
88.2
-
fsq
176.4
-
tLRH 1/128fs
-
tLRL 1/128fs
-
54
kHz
108
kHz
216
kHz
-
nsec
-
nsec
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
Double Speed Mode
High time
Low time
fsn
30
-
fsd
-
-
tLRH 1/256fs
-
tLRL 1/256fs
-
54
kHz
108
kHz
-
nsec
-
nsec
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
High time
Low time
fsn
30
-
tLRH 1/512fs
-
tLRL 1/512fs
-
54
kHz
-
nsec
-
nsec
Note 38. Normal operation is not guaranteed if a frequency not shown above is input to the LRCK when
the AK4492 is in Sampling Frequency Auto Detect Mode.
016011073-E-00
- 27 -
2016/12