AK4492ECB Datasheet, PDF (72/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
(2) Register Control Mode (PSN pin= “L”)
A register access becomes available after the PDN pin = “H”. The analog circuit starts operation by
supplying necessary clocks (MCLK, LRCK and BICK for PCM mode, MCLK and DCLK for DSD mode,
MCLK, BCK and WCK for EXDF mode) and the clock divider is powered up about after 4/fs. The analog
output pins output analog common voltages (VCML, VCMR) in this time. Then the AK4492 transitions to
normal operation by setting RSTN bit = “1”. When power up the AK4492 with the LDOE pin = “H”, 3.3V
power supplies (AVDD and TVDD) should be powered up before or at the same time of 5V power
supplies (VDDL/R).
Power
(TVDD,AVDD)
Power
(VDDL/R)
Analog Reference
(VREFHL/R)
PDN pin
(2)
DVDD pin
Internal PDN
(3)
RSTN bit
Internal State
(Resister
(Clock devider)
(9)
Power Off
Internal State
(Digital Core)
DAC In
(Digital)
(10)
Power Off
DAC Out
(5)
(6)
(Analog)
Clock In
MCLK,LRCK,BICK
DZFL/R
(1)
Don’t Care
Normal Operation
Normal Operation
“0”data
GD ⁽⁴⁾
Power Off
(10)
Power Off
“0”data
GD
(6)
(5)
(11)
(1)
(8)
External
Mute
(9)
Mute ON
Mute ON
Figure 55. Power-down/up Sequence Example (Resister Control Mode, LDOE pin= “H”)
Notes:
(1) Do not input a clock when power supplies are powered down.
(2) The PDN pin must be held “L” for more than 150ns after AVDD, TVDD and VDDL/R reached
90%.
(3) Internal LDO is powered up after the PDN pin = “H” when the LDOE pin= “H”. The internal
circuit will starts operation after the shutdown switch is ON (max. 2ms) following the internal
oscillator count up.
(4) The analog output corresponding to the digital input has group delay (GD).
(5) Analog outputs are floating (Hi-Z) in power down mode.
(6) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(7) Mute the analog output externally if click noise (6) adversely affect system performance.
(8) The DZFL/R pin is “L” in power-down mode (PDN pin = “L”).
(9) The clock divider is powered up in about 4/fs after the internal PDN is released.
(10) It takes 3~4/fs until a reset instruction is valid when writing RSTN bit to “0” and it takes
2~3/fs when releasing the reset.
(11) Clock inputs (MCLK, BICK and LRCK) can be stopped in power down state.
016011073-E-00
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2016/12