AK4492ECB Datasheet, PDF (42/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
Table 9. System Clock Example 2 (Auto Setting Mode @Pin Control Mode)
LRCK
MCLK (MHz)
Fs
256fs
384fs
512fs
768fs
1024fs
1152fs
32.0 kHz 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640
44.1 kHz 11.2896 16.9344 22.5792 33.8688
N/A
N/A
48.0 kHz 12.2880 18.4320 24.5760 36.8640
N/A
N/A
88.2 kHz 22.5792 33.8688
N/A
N/A
N/A
N/A
96.0 kHz 24.5760 36.8640
N/A
N/A
N/A
N/A
176.4 kHz
N/A
N/A
N/A
N/A
N/A
N/A
192.0 kHz
N/A
N/A
N/A
N/A
N/A
N/A
384 kHz
N/A
N/A
N/A
N/A
N/A
N/A
768 kHz
N/A
N/A
N/A
N/A
N/A
N/A
(N/A: Not available)
Sampling
Speed
Normal
Double
Quad
Oct
Hex
When MCLK= 256fs/384fs, auto setting mode supports sampling rate of 8kHz~96kHz (Table 10).
However, the DR and S/N performances will degrade approximately 3dB as compared to when MCLK =
256fs/384fs for DR and MCLK= 512fs/768fs for S/N, respectively if the sampling rate is under 54kHz.
Table 10. DR and S/N Relationship with MCLK Frequency (fs = 44.1kHz)
ACKS pin
MCLK
DR, S/N
L
256fs/384fs/512fs/768fs
123 dB
H
256fs/384fs
120 dB
H
512fs/768fs
123 dB
Note 47. This Characteristic is supported by using External Circuit (Figure 74)
016011073-E-00
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2016/12