AK4492ECB Datasheet, PDF (88/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
06H DSD1
DDM
DML
DMR
DMC DMRE
0
DSDD DSDSEL0
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
DSDSEL[1:0]: DSD data stream select
Table 21. DSD Data Stream Select
DSDSEL1 DSDSEL0
fs = 32 kHz
DSD Data Stream
fs = 44.1 kHz
fs = 48 kHz
0
0
2.048 MHz
2.8224 MHz
3.072 MHz (default)
0
1
4.096 MHz
5.6448 MHz
6.144 MHz
1
0
8.192 MHz
11.2896 MHz
12.288 MHz
1
1
N/A
N/A
N/A
DSDD: DSD Playback Path Select
Table 22. DSD Playback Path Select
DSDD
Mode
0
Normal Path (default)
1
Volume Bypass
DMRE: DSD Mute Release
0: Hold (default)
1: Release Mute
This register is only valid when DDM bit = “1” and DMC bit = “1”. When the AK4492 mutes
DSD data by DDM and DMC bits settings, the mute is released by setting DMRE bit to “1”.
Table 39. Recovery Method to Normal Operation Mode from Full Scale Detection Status
DDM DMC DMRE
Status After Detection
0
x
x
When full scale is detected, Mute function is disabled.
(default)
When full scale is detected, Mute function is enabled.
1
0
x
The AK4492 returns to normal operation automatically by a
normal signal input.
When full scale is detected, Mute function is enabled.
1
1
0
The AK4492 keeps mute mode, even if a normal signal is
input.
1
1
1
(Note 53)
When full scale is detected, Mute function is enabled.
The AK4492 returns to normal operation when a normal
signal is input and DMRE bit is set to “1”.
(x: Don not care)
Note 53. DMRE bit returns to “0” automatically after the AK4492 returns to normal operation.
DMC: DSD Mute Control
0: Auto Return (default)
1: Mute Hold (manual return)
This register is only valid when DDM bit = “1”. It selects the mute releasing mode of when the DSD
data level becomes under full-scale after the AK4492 mutes DSD data by DDM bit setting.
DMR/DML
This register outputs detection flag when a full scale signal is detected at DSDR/L channel.
DDM: DSD Data Mute
The AK4492 has an internal mute function that mutes the output when DSD audio data becomes all “1”
or all “0” for 2048 Samples (DCLK cycle). DDM bit controls this function.
0: Disable (default)
1: Enable
016011073-E-00
- 88 -
2016/12