AK4492ECB Datasheet, PDF (85/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
Addr Register Name
01H Control 2
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
DZFE DZFM
SD
DFS1 DFS0 DEM1 DEM0 SMUTE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
0
1
0
SMUTE: Soft Mute Enable
0: Normal Operation (default)
1: DAC outputs soft-muted.
DEM[1:0]: De-emphasis Control (Table 30)
Initial value is “01” (OFF).
DFS[1:0]: Sampling Speed Control. (Table 7, Table 11)
Initial value is “000” (Normal Speed). Click noise occurs when DFS[2:0] bits are changed.
SD: Minimum delay Filter Enable. (Table 28)
0: Traditional filter
1: Short delay filter (default)
DZFM: Data Zero Detect Mode
0: Channel Separated Mode (default)
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both L and R channels go to “H” only when the
input data at both channels are continuously zeros for 8192 LRCK cycles.
DZFE: Data Zero Detect Enable
0: Disable (default)
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both
channels are always “L”.
016011073-E-00
- 85 -
2016/12