AK4492ECB Datasheet, PDF (29/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
Parameter
PCM Audio Interface Timing
External Digital Filter Mode
BCK Period
BCK Pulse Width Low
BCK Pulse Width High
BCK “” to WCK Edge
WCK Period
WCK Edge to BCK “”
WCK Pulse Width Low
WCK Pulse Width High
DINL/R Hold Time
DINL/R Setup Time
Symbol Min.
Typ.
Max.
Unit
tB
27
-
tBL
10
-
tBH
10
-
tBW
5
-
tWCK
1.3
-
tWB
5
-
tWCKL
54
-
tWCKH
54
-
tDH
5
-
tDS
5
-
-
nsec
-
nsec
-
nsec
-
nsec
-
usec
-
nsec
-
nsec
-
nsec
-
nsec
-
nsec
DSD Audio Interface Timing
Sampling Frequency
fs
30
48
kHz
(64fs mode, DSDSEL [1:0] bits = “00”)
DCLK Period
tDCK
-
1/64fs
-
DCLK Pulse Width Low
tDCKL 144
-
-
DCLK Pulse Width High
tDCKH 144
-
-
DCLK Edge to DSDL/R (Note 43) tDDD
20
-
20
nsec
nsec
nsec
nsec
(128fs mode, DSDSEL [1:0] bits = “01”)
DCLK Period
tDCK
-
1/128fs
-
nsec
DCLK Pulse Width Low
tDCKL
72
-
-
nsec
DCLK Pulse Width High
tDCKH
72
-
-
nsec
DCLK Edge to DSDL/R (Note 43) tDDD
10
-
10
nsec
(256fs mode, DSDSEL [1:0] bits = “10”)
DCLK Period
tDCK
-
1/256fs
-
nsec
DCLK Pulse Width Low
tDCKL
36
-
-
nsec
DCLK Pulse Width High
tDCKH
36
-
-
nsec
DCLK Edge to DSDL/R (Note 43) tDDD
5
-
5
nsec
Note 43. DSD data transmitting device must meet this time. “tDDD” is defined from DCLK “↓” until
DSDL/R edge when DCKB bit = “0” (default), “tDDD” is defined from DCLK “↑” until DSDL/R
edge when DCKB bit = “1”. If the audio data format is in phase modulation mode, “tDDD” is
defined from DCLK edge “↓” or “↑” until DSDL/R edge regardless of DCKB bit setting.
016011073-E-00
- 29 -
2016/12