AK4492ECB Datasheet, PDF (50/101 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4492]
Table 24. Audio Interface Format
Mode
TDM1 TDM0 DIF2 DIF1 DIF0
bit bit bit bit bit
SDATA Format
LR
CK
BICK
Figure
0
0
0
0 16-bit LSB justified
H/L  32fs Figure 25
1
0
0
1 20-bit LSB justified
H/L  40fs Figure 26
2
0
1
0 24-bit MSB justified H/L  48fs Figure 27
16-bit I²S Compatible L/H 32fs
Normal ³
(Note 49)
0
0
0
1
1 _{24-bit I2S Compatible L/H  48fs} Figure 28
4
1
0
0 24-bit LSB justified
H/L  48fs Figure 26
5
1
0
1 32-bit LSB justified
H/L  64fs Figure 29
6
1
1
0 32-bit MSB justified H/L  64fs Figure 30
7
1
1
1 32-bit I²S Compatible L/H  64fs Figure 31
-
-
-
-
N/A
-
-
-
-
-
-
-
N/A
-
-
-
8
0
1
0 24-bit MSB justified H/L 128fs Figure 32
9
0
1
1 24-bit I²S Compatible L/H 128fs Figure 33
TDM128 ₁₀ 0
1
1
0
0 24-bit LSB justified
H/L 128fs Figure 34
11
1
0
1 32-bit LSB justified
H/L 128fs Figure 32
12
1
1
0 32-bit MSB justified H/L 128fs Figure 32
13
1
1
1 32-bit I²S Compatible L/H 128fs Figure 33
-
-
-
-
N/A
-
-
-
-
-
-
-
N/A
-
-
-
14
0
1
0 24-bit MSB justified H/L 256fs Figure 35
15
0
1
1 24-bit I²S Compatible L/H 256fs Figure 36
TDM256 ₁₆ 1
0
1
0
0 24-bit LSB justified
H/L 256fs Figure 37
17
1
0
1 32-bit LSB justified
H/L 256fs Figure 35
18
1
1
0 32-bit MSB justified H/L 256fs Figure 35
19
1
1
1 32-bit I²S Compatible L/H 256fs Figure 36
-
-
-
-
N/A
-
-
-
-
-
-
-
N/A
-
-
-
20
0
1
0 24-bit MSB justified H/L 512fs Figure 38
21
0
1
1 24-bit I²S Compatible L/H 512fs Figure 39
TDM512 ₂₂ 1
1
1
0
0 24-bit LSB justified
H/L 512fs Figure 40
23
1
0
1 32-bit LSB justified
H/L 512fs Figure 38
24
1
1
0 32-bit MSB justified H/L 512fs Figure 38
25
1
1
1 32-bit I²S Compatible L/H 512fs Figure 39
Note 49. BICK more than setting bit must be input to each channel. In the LRCK column, “H/L” indicates
that L channel data can be input when LRCK is “H” and R channel data can be input when LRCK
is “L”. “L/H” indicates L channel data can be input when LRCK is “L” and R channel data can be
input when LRCK is “H”.
Note 50. The default settings in Register Control Mode are shown below.
TDM1 bit = “0”, TDM0 bit = “0”, DIF2 bit = “1”, DIF1 bit = “1”, DIF0 bit = “0”
016011073-E-00
- 50 -
2016/12