AK5701_07 Datasheet, PDF (8/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP

[AK5701]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V; C_L=20pF)
Parameter
Symbol
min
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
Pulse Width Low
tCLKL 0.4/fCLK
Pulse Width High
tCLKH 0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
256fs at fs=32kHz, 29.4kHz
dMCK
-
LRCK Output Timing
Frequency
Except DSP Mode 1
fs
7.35
DSP Mode 1 (Note 18)
fsd
14.7
DSP Mode: Pulse Width High
tLRCKH
-
Except DSP Mode: Duty Cycle
Duty
-
BCLK Output Timing
Period
BCKO1-0 bit = “01”
tBCK
-
BCKO1-0 bit = “10”
tBCK
-
Duty Cycle
dBCK
-
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
Pulse Width Low
tCLKL 0.4/fCLK
Pulse Width High
tCLKH 0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
256fs at fs=32kHz, 29.4kHz
dMCK
-
EXLRCK Input Timing
Frequency
DSP Mode: Pulse Width High
fs
7.35
tLRCKH tBCK−60
Except DSP Mode: Duty Cycle
Duty
45
EXBCLK Input Timing
Period
tBCK
1/(64fs)
Pulse Width Low
tBCKL 0.4 x tBCK
Pulse Width High
tBCKH 0.4 x tBCK
PLL Slave Mode (PLL Reference Clock = EXLRCK pin)
EXLRCK Input Timing
Frequency
DSP Mode: Pulse Width High
fs
7.35
tLRCKH tBCK−60
Except DSP Mode: Duty Cycle
Duty
45
EXBCLK Input Timing
Period
tBCK
1/(64fs)
Pulse Width Low
tBCKL 0.4 x tBCK
Pulse Width High
tBCKH 0.4 x tBCK
typ
-
-
-
-
50
33
-
-
tBCK
50
1/(32fs)
1/(64fs)
50
-
-
-
-
50
33
-
-
-
-
-
-
-
-
-
-
-
-
Note 18. Sampling frequency is 7.35kHz ∼ 48kHz.
max
Units
27
-
-
12.288
60
-
MHz
ns
ns
MHz
%
%
48
kHz
96
kHz
-
ns
-
%
-
ns
-
ns
-
%
27
MHz
-
ns
-
ns
12.288 MHz
60
%
-
%
48
kHz
1/fs − tBCK ns
55
%
1/(32fs)
ns
-
ns
-
ns
48
kHz
1/fs − tBCK ns
55
%
1/(32fs)
ns
-
ns
-
ns
MS0404-E-02
-8-
2007/08