AK5701_07 Datasheet, PDF (42/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP

[AK5701]
■ Register Definitions
Addr
10H
Register Name
Power Management
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
PMVCM PMADR PMADL
0
0
0
0
0
0
0
0
PMADL: MIC-Amp Lch and ADC Lch Power Management
0: Power down (default)
1: Power up
PMADR: MIC-Amp Rch and ADC Rch Power Management
0: Power down (default)
1: Power up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (3088/fs=70.0ms@fs=
44.1kHz, HPF1-0 bits = “00”) starts. After initializing, digital data of the ADC is output.
PMVCM: VCOM Power Management
0: Power down (default)
1: Power up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when PMADL=PMADR=PMPLL=PMMP=MCKO bits = “0”.
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When PMVCM, PMADL, PMADR, PMPLL and MCKO bits are “0”, all blocks are powered-down. The register
values remain unchanged. Power supply current is 20μA(typ) in this case. For fully shut down (typ. 1μA), the PDN pin
should be “L”.
When the ADC is not used, external clocks may not be present. When ADC is used, external clocks must always be
present.
Addr
11H
Register Name
PLL Control
Default
D7
D6
0
0
0
0
PMPLL: PLL Power Management
0: EXT Mode and Power Down (default)
1: PLL Mode and Power up
M/S: Master / Slave Mode Select
0: Slave Mode (default)
1: Master Mode
PLL3-0: PLL Reference Clock Select (Table 4)
Default: “1001”(MCKI pin=12MHz)
D5
PLL3
1
D4
PLL2
0
D3
PLL1
0
D2
PLL0
1
D1
D0
M/S PMPLL
0
0
MS0404-E-02
- 42 -
2007/08