AK5701_07 Datasheet, PDF (27/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP

[AK5701]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”, TE3-0 bits = “0101”, TMASTER bit = “1”)
The AK5701 becomes EXT Master Mode by setting as Figure 49. Master clock is input from the MCKI pin, the internal
PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The input frequency of
MCKI is selected by FS1-0 bits (Table 12).
Mode
0
1
2
3
FS3-2 bits
FS1 bit FS0 bit
MCKI Input
Frequency
Sampling Frequency
Range
x
0
0
256fs
7.35kHz ∼ 48kHz
x
0
1
1024fs
7.35kHz ∼ 13kHz
x
1
0
512fs
7.35kHz ∼ 26kHz
x
1
1
256fs
7.35kHz ∼ 48kHz
Table 12. MCKI Frequency at EXT Master Mode (x: Don’t care)
(default)
MCKI should always be present whenever the ADC is in operation (PMADL bit = “1” or PMADR bit = “1”). If MCKI is
not provided, the AK5701 may draw excess current and it is not possible to operate properly because utilizes dynamic
refreshed logic internally. If MCKI is not present, the ADC should be in the power-down mode (PMADL=PMADR bits
= “0”).
AK5701
MCKO
MCKI
BCLK
LRCK
SDTO
256fs, 512fs or 1024fs
32fs or 64fs
DSP or μP
MCLK
BCLK
1fs
LRCK
SDTI
Figure 23. EXT Master Mode
BCKO1 bit BCKO0 bit
BCLK Output
Frequency
0
0
N/A
0
1
32fs
(default)
1
0
64fs
1
1
N/A
Table 13. BCLK Output Frequency at Master Mode (N/A: Not available)
MS0404-E-02
- 27 -
2007/08