AK5701_07 Datasheet, PDF (47/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP

[AK5701]
SYSTEM DESIGN
Figure 43 and Figure 44 shows the system connection diagram for the AK5701. The evaluation board [AKD5701]
demonstrates the optimum layout, power supply arrangements and measurement results.
μP
External MIC
Internal MIC
0.1 x Cp
(Note)
≤ 1u
≤ 1u
≤ 1u
≤ 1u
Rp
Cp
19 MPWR
20 RIN2
21 LIN2
22 RIN1
23 LIN1
24 VCOC
AK5701
Top View
EXLRCK 12
EXSDTI 11
MCKO 10
CSP 9
SDTO 8
LRCK 7
DSP
DSP
Power Supply
2.4 ∼ 3.6V
Power Supply
1.6 ∼ 3.6V
Analog Ground
Digital Ground
Notes:
- AVSS and DVSS of the AK5701 should be distributed separately from the ground of external controllers.
- All digital input pins should not be left floating.
- When the AK5701 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of the VCOC pin is not needed.
- When the AK5701 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of the VCOC pin is shown in Table
4. 0.1 x Cp in parallel with Cp+Rp improves PLL jitter characteristics.
- Mic input AC coupling capacitor should be 1μF or less to start the recording within 100ms.
Figure 43. Typical Connection Diagram (MIC Input)
MS0404-E-02
- 47 -
2007/08