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AK5701_07 Datasheet, PDF (43/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP | |||
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[AK5701]
Addr
12H
Register Name
Signal Select
Default
D7
D6
0
0
0
0
D5
D4
D3
D2
D1
D0
0
PMMP MDIF2 MDIF1
INR
INL
0
0
0
0
0
0
INL: ADC Lch Input Source Select
0: LIN1 pin (default)
1: LIN2 pin
INR: ADC Rch Input Source Select
0: RIN1 pin (default)
1: RIN2 pin
MDIF1: ADC Lch Input Type Select
0: Single-ended input (LIN1/LIN2 pin: default)
1: Full-differential input (LIN+/LINâ pin)
MDIF2: ADC Rch Input Type Select
0: Single-ended input (RIN1/RIN2 pin: default)
1: Full-differential input (RIN+/RINâ pin)
PMMP: MPWR pin Power Management
0: Power down: Hi-Z (default)
1: Power up
Addr
13H
Register Name
Mic Gain Control
Default
D7
D6
D5
D4
D3
0
0
0
0
0
0
0
0
0
0
D2
D1
D0
0
MGAIN1 MGAIN0
0
0
1
MGAIN1-0: MIC-Amp Gain Control (Table 20)
Default: â01â(+15dB)
Addr
14H
Register Name
Audio Format Select
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
MIX MSBS BCKP DIF1
DIF0
0
0
1
0
0
0
1
1
DIF1-0: Audio Interface Format (Table 15)
Default: â11â (I2S)
BCKP: BCLK/EXBCLK Polarity at DSP Mode (Table 16)
â0â: SDTO is output by the rising edge (âââ) of BCLK/EXBCLK. (default)
â1â: SDTO is output by the falling edge (âââ) of BCLK/EXBCLK.
MSBS: LRCK/EXLRCK Polarity at DSP Mode (Table 16)
â0â: The rising edge (âââ) of LRCK/EXLRCK is half clock of BCLK/EXBCLK before the channel change.
(default)
â1â: The rising edge (âââ) of LRCK/EXLRCK is one clock of BCLK/EXBCLK before the channel change.
MIX: ADC Output Data Select (Table 17)
â0â: Normal operation (default)
â1â: (L+R)/2
MS0404-E-02
- 43 -
2007/08
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