AK5701_07 Datasheet, PDF (24/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP

[AK5701]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz)
is input to MCKI pin, the MCKO, BCLK and LRCK clocks are generated by an internal PLL circuit. The MCKO output
frequency is selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit. The BCLK output frequency is
selected among 32fs or 64fs, by BCKO1-0 bits (Table 10).
AK5701
11.2896MHz, 12MHz, 12.288MHz, 13MHz
13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
DSP or μP
MCKI
MCKO
BCLK
LRCK
SDTO
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTI
Figure 19. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
(default)
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BCKO1 bit BCKO0 bit
BCLK Output
Frequency
0
0
N/A
0
1
32fs
(default)
1
0
64fs
1
1
N/A
Table 10. BCLK Output Frequency at Master Mode (N/A: Not available)
MS0404-E-02
- 24 -
2007/08