AK5701_07 Datasheet, PDF (23/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP

[AK5701]
When PLL reference clock input is EXLRCK or EXBCLK pin, the sampling frequency is selected by FS3 and FS2 bits
(Table 6).
Mode ^{FS3 bit FS2 bit}
FS1 bit
FS0 bit
Sampling Frequency
Range
0
0
0
x
1
0
1
x
x
7.35kHz ≤ fs ≤ 12kHz
x
12kHz < fs ≤ 24kHz
2
1
x
x
x
24kHz < fs ≤ 48kHz
(default
)
Others
Others
N/A
(x: Don’t acre, N/A: Not available)
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” and Reference=EXLRCK/EXBCLK
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BCLK pins go to “L” and irregular frequency clock is output from the MCKO pin at MCKO bit
is “1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, the MCKO pin changes to “L”
(Table 7).
In DSP Mode 0 and 1, BCLK and LRCK start to output corresponding to Lch data after PLL goes to lock state by setting
PMPLL bit = “0” Æ “1”. When MSBS and BCKP bits are “01” or “10” in DSP Mode 0 and 1, BCLK “H” time of the first
pulse becomes 1/(256fs) shorter than “H” time except for the first pulse.
When sampling frequency is changed, BCLK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
PLL State
After that PMPLL bit “0” Æ “1”
PLL Unlock (except above case)
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
Invalid
“L” Output
Invalid
BCLK pin
“L” Output
Invalid
PLL Lock
“L” Output
See Table 9
See Table 10
Note 30. LRCK becomes 2fs at DSP Mode 1.
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
LRCK pin
“L” Output
Invalid
1fs Output
(Note 30)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ
“1”. After that, the clock selected by Table 9 is output from the MCKO pin when PLL is locked. ADC and DAC output
invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL, DACH and
DACS bits.
PLL State
After that PMPLL bit “0” Æ “1”
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
Invalid
PLL Unlock (except above case)
“L” Output
Invalid
PLL Lock
“L” Output
See Table 9
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MS0404-E-02
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2007/08