AK5701_07 Datasheet, PDF (59/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP

[AK5701]
3. PLL Slave Mode (MCKI pin)
PMPLL bit
(Addr:11H, D0)
MCKO bit
(Addr:16H, D2)
External MCKI
(1)
(2)
(3)
Input
Example
Audio I/F Format: I2S
PLL Reference clock: MCKI= 11.2896MHz
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
(1) Addr:11H, Data:10H
(2) Addr:16H, Data:00H
(3) Stop the external clocks
Figure 55. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO output: MCKO bit = “1” → “0”
(3) Stop the external master clock.
4. EXT Slave Mode
External MCKI
EXBCLK
EXLRCK
Input
Input
Input
(1)
Example
(1)
Audio I/F Format :I2S
Input MCKI frequency:256fs
Sampling Frequency:44.1kHz
(1)
(1) Stop the external clocks
Figure 56. Clock Stopping Sequence (4)
<Example>
(1) Stop the external MCKI, EXBCLK and EXLRCK clocks.
* Clock stop sequence is the same for Bypass Mode.
5. EXT Master Mode
External MCKI
BCLK
LRCK
Input
Output
Output
(1)
"H" or "L"
"H" or "L"
Example
Audio I/F Format :I2S
Input MCKI frequency:256fs
Sampling Frequency:44.1kHz
(1) Stop MCKI
Figure 57. Clock Stopping Sequence (5)
<Example>
(1) Stop MCKI. BCLK and LRCK are fixed to “H” or “L”.
MS0404-E-02
- 59 -
2007/08