AK5701_07 Datasheet, PDF (44/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP

[AK5701]
Addr
15H
Register Name
fs Select
Default
D7
D6
D5
D4
D3
D2
D1
D0
HPF1
HPF0 BCKO1 BCKO0 FS3
FS2
FS1
FS0
0
0
0
1
1
1
1
1
FS3-0: Sampling Frequency Select (Table 5 and Table 6) and MCKI Frequency Select (Table 11)
Default: “1111” (44.1kHz)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
BCKO1-0: BCLK Output Frequency Select at Master Mode (Table 10)
Default: “01” (32fs)
HPF1-0: Offset Cancel HPF Cut-off Frequency and ADC Initialization Cycle (Table 18, Table 30)
Default: “00” (fc=3.4Hz@fs=44.1kHz, Init Cycle=3088/fs)
Addr
16H
Register Name
Clock Output Select
Default
D7
D6
D5
0
0
0
0
0
0
PS1-0: MCKO Output Frequency Select (Table 9)
Default: “00”(256fs)
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
THR: Bypass Mode (Table 14)
0: OFF (default)
1: ON
D4
D3
D2
D1
D0
0
THR MCKO PS1
PS0
0
0
0
0
0
Addr
17H
Register Name
Volume Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
IVOLC
0
0
0
0
0
0
0
1
IVOLC: Input Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0
bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits
control Rch level, respectively.
Addr
18H
19H
Register Name
Lch Input Volume Control
Rch Input Volume Control
Default
D7
IVL7
IVR7
1
D6
IVL6
IVR6
0
D5
IVL5
IVR5
0
D4
IVL4
IVR4
1
D3
IVL3
IVR3
0
IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 29)
Default: “91H” (0dB)
D2
IVL2
IVR2
0
D1
IVL1
IVR1
0
D0
IVL0
IVR0
1
MS0404-E-02
- 44 -
2007/08