AK5701_07 Datasheet, PDF (28/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP

[AK5701]
■ Bypass Mode
When THR bit = “1”, M/S bit = “0”, PMADL bit = “0” and PMADR bit = “0”, input clocks and data of EXLRCK,
EXBCLK and EXSDTI pins are bypassed to LRCK, BCLK and SDTO pins, respectively.
When THR bit = “1”, M/S bit = “0” and PMADL bit = “1” or PMADR bit = “1”, input clocks of EXLRCK and EXBCLK
pins are bypassed to LRCK and BCLK pins, and ADC data is output from the SDTO pin.
THR bit M/S bit
0
0
1
0
1
1
PMADL bit
PMADR bit
BCLK/LRCK
SDTO
Mode
00
L
L
Power down
01/10/11
L
ADC data Slave mode
00
Output
L
Power down
01/10/11
Output
ADC data Master mode
00
EXBCLK/EXLRCK EXSDTI Bypass mode
01/10/11
EXBCLK/EXLRCK ADC data Slave & Bypass
00
N/A
N/A
N/A
01/10/11
Output
ADC data Master mode
Table 14. Bypass Mode Select (N/A: Not available)
Figure
Figure 24
Figure 25
(default
)
DSP or μP
BCLK
LRCK
SDTI
DSP or μP
BCLK
LRCK
SDTI
≥ 32fs
1fs
AK5701
BCLK
LRCK
SDTO
EXBCLK
EXLRCK
EXSDTI
≥ 32fs
1fs
≥ 32fs
1fs
Figure 24. Bypass Mode
AK5701
BCLK
LRCK
SDTO
EXBCLK
EXLRCK
LIN/RIN
≥ 32fs
1fs
Analog In
Figure 25. Slave & Bypass Mode
DSP or μP
BCLK
LRCK
SDTO
DSP or μP
BCLK
LRCK
MS0404-E-02
- 28 -
2007/08