AK5701_07 Datasheet, PDF (29/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP

[AK5701]
■ Audio Interface Format
Fore types of data format are available and are selected by setting the DIF1-0 bits (Table 15). In all modes, the serial data
is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes, but DSP Mode
1 supports PLL Master Mode only. LRCK, BCLK and SDTO pins are used in master mode. EXLRCK, EXBCLK and
SDTO pins are used in slave mode. In modes 2 and 3, the SDTO is clocked out on the falling edge (“↓”) of
BCLK/EXBCLK.
Mode
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
SDTO
BCLK, EXBCLK
DSP Mode 0
32fs
DSP Mode 1
≥ 32fs
MSB justified
I²S compatible
≥ 32fs
≥ 32fs
Table 15. Audio Interface Format
Figure
See Table 16
Figure 34
Figure 35 (default)
In Modes 0 and 1 (DSP mode 0 and 1), the audio I/F timing is changed by BCKP and MSBS bits.
When BCKP bit is “0”, SDTO data is output by rising edge (“↑”) of BCLK/EXBCLK.
When BCKP bit is “1”, SDTO data is output by falling edge (“↓”) of BCLK/EXBCLK.
MSB data position of SDTO can be shifted by MSBS bit. The shifted period is a half of BCLK/EXBCLK.
DIF1
0
0
DIF0
0
1
MSBS
0
0
1
1
0
0
1
1
BCKP
0
1
0
1
0
1
0
1
Audio Interface Format
MSB of SDTO is output by the rising edge (“↑”) of the first
BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK (Figure
26).
MSB of SDTO is output by the falling edge (“↓”) of the first
BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK (Figure
27).
MSB of SDTO is output by next rising edge (“↑”) of the falling edge (“↓”)
of the first BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
(Figure 28).
MSB of SDTO is output by next falling edge (“↓”) of the rising edge (“↑”)
of the first BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
(Figure 29).
MSB of SDTO is output by the rising edge (“↑”) of the first
BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK (Figure
30).
MSB of SDTO is output by the falling edge (“↓”) of the first
BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK (Figure
31).
MSB of SDTO is output by next rising edge (“↑”) of the falling edge (“↓”)
of the first BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
(Figure 32).
MSB of SDTO is output by next falling edge (“↓”) of the rising edge (“↑”)
of the first BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
(Figure 33).
Table 16. Audio Interface Format in Mode 0, 1
(default)
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
MS0404-E-02
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2007/08