|
AK5701_07 Datasheet, PDF (31/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP | |||
|
◁ |
[AK5701]
LRCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BCLK(32fs)
Lch
Rch
SDTO(o)
0 15 14 8 8 7 6 5 4 3 2 1 0 15 14 8 8 7 6 5 4 3 2 1 0
15
BCLK(64fs)
SDTO(o)
0 1 2 8 14 15 16 17 18 29 30 31
Lch
15 14 8 2 1 0
0 1 2 8 14 15 16 17 18 13 30 31
Rch
15 14 8 2 1 0
1/fs
15:MSB, 0:LSB
Figure 30. Mode 1 Timing (BCKP = â0â, MSBS = â0â, M/S = â1â)
LRCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BCLK(32fs)
Lch
Rch
SDTO(o)
0 15 14 8 8 7 6 5 4 3 2 1 0 15 14 8 8 7 6 5 4 3 2 1 0
15
BCLK(64fs)
SDTO(o)
0 1 2 8 14 15 16 17 18 29 30 31
Lch
15 14 8 2 1 0
0 1 2 8 14 15 16 17 18 13 30 31
Rch
15 14 8 2 1 0
1/fs
15:MSB, 0:LSB
Figure 31. Mode 1 Timing (BCKP = â1â, MSBS = â0â, M/S = â1â)
LRCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BCLK(32fs)
Lch
Rch
SDTO(o)
0 15 14 8 8 7 6 5 4 3 2 1 0 15 14 8 8 7 6 5 4 3 2 1 0
15
BCLK(64fs)
SDTO(o)
0 1 2 8 14 15 16 17 18 29 30 31
Lch
15 14 8 2 1 0
0 1 2 8 14 15 16 17 18 13 30 31
Rch
15 14 8 2 1 0
1/fs
15:MSB, 0:LSB
Figure 32. Mode 1 Timing (BCKP = â0â, MSBS = â1â, M/S = â1â)
LRCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BCLK(32fs)
Lch
Rch
SDTO(o)
0 15 14 8 8 7 6 5 4 3 2 1 0 15 14 8 8 7 6 5 4 3 2 1 0
15
BCLK(64fs)
SDTO(o)
0 1 2 8 14 15 16 17 18 29 30 31
Lch
15 14 8 2 1 0
0 1 2 8 14 15 16 17 18 13 30 31
Rch
15 14 8 2 1 0
1/fs
15:MSB, 0:LSB
Figure 33. Mode 1 Timing (BCKP = â1â, MSBS = â1â, M/S = â1â)
MS0404-E-02
- 31 -
2007/08
|
▷ |