AK5701_07 Datasheet, PDF (11/64 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP

[AK5701]
Parameter
Symbol
min
Control Interface Timing (CSP pin = “L”)
CCLK Period
tCCK
142
CCLK Pulse Width Low
tCCKL
56
Pulse Width High
tCCKH
56
CDTI Setup Time
tCDS
28
CDTI Hold Time
tCDH
28
CSN “H” Time
CSN Edge to CCLK “↑” (Note 22)
CCLK “↑” to CSN Edge (Note 22)
tCSW
150
tCSS
50
tCSH
50
Control Interface Timing (CSP pin = “H”)
CCLK Period
tCCK
142
CCLK Pulse Width Low
tCCKL
56
Pulse Width High
tCCKH
56
CDTI Setup Time
tCDS
28
CDTI Hold Time
tCDH
28
CSN “L” Time
CSN Edge to CCLK “↑” (Note 22)
CCLK “↑” to CSN Edge (Note 22)
tCSW
150
tCSS
50
tCSH
50
Power-down & Reset Timing
PDN Pulse Width (Note 23)
tPD
150
PMADL or PMADR “↑” to SDTO valid (Note 24)
HPF1-0 bits = “00”
tPDV
-
HPF1-0 bits = “01”
tPDV
-
HPF1-0 bits = “10”
tPDV
-
Note 22. CCLK rising edge must not occur at the same time as CSN edge.
Note 23. The AK5701 can be reset by the PDN pin = “L”.
Note 24. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3088
1552
784
max
Units
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
1/fs
-
1/fs
-
1/fs
MS0404-E-02
- 11 -
2007/08