AK7712A-VT Datasheet, PDF (78/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
[AK7712A-VT]
3)Action of DSP Unit, at Reset
This LSI has two kinds of reset; "reset(RST)" and "power down(PD)". If RST is set to "L"(PD ="H"), each register is
reset, and PRAM,CRAM and OFRAM become write enable state. If RST is set to "H"(PD="H"), the reset is
cancelled, and the external RAM clear("0" data write) and the write data"0" to internal DRAM are executed from the
rising edge of LRCK. this period takes 2260*1/fs [sec](fs: sampling frequency). In periods of reset and of write
"0"data to DRAM, input/output data is operates as "0". In these periods, DZF is kept "H". These period take
51.3msec at 44.1kHz(384fs). To be disable this function, set control register C19 to "1".This timing is shown in
Fig.45.
Fig.45 Timing at Reset and after Cancellation of Reset
If both of RST and PD are set to "L", this LSI becomes power down state, so the control register is also reset to
default state. After cancellation, it actions same above. To change the control register or program, set PD to "H", load
data, set RST to "H".
Fig.46 Timing at Power Down and after Cancellation of Reset
0180-E-02
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1997/12