AK7712A-VT Datasheet, PDF (40/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
„ Data RAM(DRAM)
[AK7712A-VT]
Data RAM is written through the DBUS, and is read on multiplier and DBUS directly. The capacity of memory is 128
word × 24 bit, and two memory pointers are prepared. The pointers of DP0 and DP1 are used after setting to
command register from outside before starting. The two method of addressing are prepared, the linear-addressing
method which starts with DP0:00H and DP1: 40H, and the ring-addressing method which increases start address
for every sampling cycle. When this ring-addressing is chosen, the address is added "1" for every sampling (start of
DP0 address:00→01→02→03→04^……). The starting pointer appointment for every sampling cycle is chosen to
DP0. The address is able to increment(+1,+2,+3) and to decrement(-1,-2,-3). By load command, it is able to load the
DBUS data directly as pointer value. On using this load command, or loading DBUS data to pointer, the
value(loaded value + starting address at ring addressing method, loaded value at linear-addressing method) is
loaded to pointer. DPC command executes the change of pointer, at the same time the increment of changed
pointer. For example , when the pointer is changed from DP0 to DP1, not only the change of DP0→DP1 but also the
increment of address of DP0 are done. The timing of it is shown below.
<The List of DRAM Relational Command>
DPC: change pointer(DP0→DP1,DP0+1 ; DP1→DP0,DP1+1)
DU1: address+1 DD1: address-1
DU2: address+2 DD2: address-2
DU3: address+3 DD3: address-3
DRAM: output the data to DBUS(at the same time to selector of multiplier)
@DP0: load the DBUS data to DRAM-CP0 pointer
@DP1: load DBUS data to DRAM-CP1 pointer
@DRAM: write DBUS data
0180-E-02
- 40 -
1997/12