AK7712A-VT Datasheet, PDF (33/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
[AK7712A-VT]
SDLF and BDRF take a peculiar action to calculate 45 × 31 and 45 × 16. The example program is shown on section
2) Multiplier. SDLF shifts the lower 15 bits of the product to 15 bits left, and calculates the 34 bits data, whose upper
13 bits and lower 6 bits are "0". The lower 6 bits of the product are set to "0" at next step.
BDRF shifts the 13 bits from upper extended data of DR0 to 15 bits right as input data, and extends this 19-bit data
from MSB for 15 bits upper, and then calculate 34-bit data, which is set the lower 6 bits to "0".
In this command, although not appoint DR register, DR0 data is chose and is added to upper data register.
(By hardware, the output of DR0 is directly connected to shift.)
• • • • _ABCDEF• • •
4-bit extension
↓shift to 15 bits right
••• ••• ••• ••• ••• ••• •_{A B C D} ••• •_{0 0 0 0 0 0}
lower 6 bits ="0"
15-bit extension of MSB (extend from MSB of the extended 4 bits)
In addition to the direct shift command by the program mentioned above, the indirect shift, which execute with shift
number set to indirect shift command circuit, is prepared. The relation of shift and shift number is shown as following
colum. This circuit is connected with upper 5 bits of DBUS, and is set value by @SHR command, and then is carried
out in next step, taking priority of shift field command. Using this function and peak detection in P.44, the data can be
regulated. (ex. 163AFE(HEX) → 58EBF8(HEX)) The example of program is shown as follows. (assuming that DR0
is regulated.)
,OP,,
,OP,,
,PP,,IDR0=BH0 <<
<Example of Data Regulating>
,,,,ODR0 ,@PDR ;detecting size of DR0
,,,,PDR ,@SHR ;setting shift number with indirect shift
,,,,ODR0 ,
;execution of indirect shift taking priority of BH0 after 1 step.
0180-E-02
- 33 -
1997/12