AK7712A-VT Datasheet, PDF (71/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
7) Timing with Microcomputer
[AK7712A-VT]
In case of transferring data from microcomputer, the command data can be input on condition that the WRQ is set to
"H", the command register is reset and WRQ is set to "L". CS must be set to "L" in case of receiving/ transferring
data from/to this LSI. If CS is set to "H", then SO and WRDY become "Hi-z" state and can not receive/transform
data. The timing of data load at reset(RST ="L", PD ="Hi") is shown in Fig.38 and 39. If the transferring data is
finished then WRDY signal becomes "L", and if down load is finished then it return to "H".
The motion transferring next data is suppressed in that period(WRDY= "L"). Since the period has short length about
2 cycles of master clock, if SCLK is slow enough then monitoring of WRDY is not needed.
Fig.38 Input of Continuos Address Data to PRAM,CRAM and OFRAM
Fig.39 Input of Discontinuos Address Data to PRAM,CRAM and OFRAM
0180-E-02
- 71 -
1997/12