AK7712A-VT Datasheet, PDF (37/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
[AK7712A-VT]
5) Division
The divider is equipped with a circuit independently. The condition and format of data are as follows.
Input data: A= dividient (16-bit)
: B= divisor (16-bit)
Output data: Q= quotient (16-bit)
Condition: 0<A<B ; A and B are positive, and Q is less than 1.
If input data is set in such order @DIVA,@DIVB on SRC field, the operation begins automatically, and the quotient is
obtained after 17 steps from @DIVB command, the result is held until the next direction of division. Then the data
output is available on and after 18th step. In this division, other calculation can be done. In such case, the order
@DIVA,@DIVB must be kept for operating division even if the same dividient or divisor data is used.
6) Pink noise generator circuitry
The single repatriated shift resistors [24, 21, 19, 18, 17, 16, 15, 14, 13, 10, 9, 5, 1]s are independently equipped in
this device apart from the arithmetic function block.
This circuitry renews the data at every sampling cycle and output data is connected to DBUS. As a result, the value
for 24bit can be asked at the sampling cycle when MRSG are pointed out in the DST field.
Besides, in case of use of pink noise generator circuitry, C5 should be set to 1 when control resistors are set.
0180-E-02
- 37 -
1997/12