AK7712A-VT Datasheet, PDF (45/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
„ DBUS(Data BUS)
[AK7712A-VT]
When output data to DBUS is less than 24 bits, the "0" data is supplemented from LSB side. Except @IORL
command, all input from DBUS is taken out the needed data length from MSB side. The @IORL inputs lower 8 bits
of DBUS data. When SRC field is NON or reset state, DBUS is set to "L".
„ Sequence Control Unit
It consists of 384word×32-bit PRAM(SRAM), micro program sequencer, 5-bit loop counter, 24-bit BUS inter-
connection, 8-bit return address register and 8-bit external condition register(IFCON). the writing data to PRAM,
which stores 32-bit horizontal macro command, is loaded at reset of DSP unit by such as microcomputer. By this 32-
bit horizontal micro command, the command is read at calculation command, and multiplication, addition,
subtraction and data transfer are operated in parallel. The micro program sequencer consists of 9-bit program
counter, 1 level stack register, pipeline instruction register and instruction decoder, LOOP, CAL, JMP, END,
conditional JMP, external conditional jump and load are executed. The stack is 9-bit and 1 level, and stores the
return address when subroutine call command is executed. By using this subroutine and LOOP, although program
capacity is 384 word, can be done 574 steps of operation at maximum when master clock is 576fs (sampling
frequency is 32kHz only). Using this feature, the loop command is convenience for reading/writing of external RAM.
As the stack is 1 level, it is not able to make call/loop command in the call/loop sentence. But conditional jump is
able to use in subroutine. When you make the program in that the jump is not return to the return address in call
sentence, AKM can not guarantee how does this DSP's action. This is same in loop command. At using that, it can
not return to the address stacked at call command. The BUS inter-connection between PBUS and DBUS realizes
that the 24-bit data is done the literal load to each register on DBUS by instruction. All sequence commands are 1
word commands(32-bit), and the time taken from the output of program counter to the end of command execution is
different in each command, but most of this is taken 2∼3 machine cycles. The timing of each instructions are shown
below.
, Jump
The timing of jump is shown in the figure below. As the figure shows, 1 machine cycle of NOP is inserted
before jumping from the address of jump command to appointed address.
0180-E-02
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1997/12