AK7712A-VT Datasheet, PDF (74/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
[AK7712A-VT]
SO can output the data on DBUS of this LSI. By appointing @MICR at DST field, the data is set, and DRDY
becomes to "H", and the data is put synchronizing with falling edge of SCLK. If once CS is changed to "H", DRDY
becomes to "L", and wait the next command. If once DRDY becomes to "H", the data of first @MICR command after
DRDY="H" is held and other command is not received while CS is held "L".In case of output from SO, set WRQ to
"H", and CS to "L".
Fig.44 Output Timing of SO
* Attentions concerning of control signal for micro computer interface
Control signal for micro computer interface(CS, RST, WRQ should be allowed to change when SCLK is in "H" state.
* SO output is maximum 24bit data. After obtaining the indispensable number of data(less than 24), the subsequent
data can be possible to output when CS is in "H" state.
„ High-pass Filter
AK7712A has digital high-pass filter(HPF) for DC offset cancel. HPF is active when control register C6 is "0". The
cut-off frequency of HPF is about 1Hz(fs=48kHz). If C6 is set to "1" then HPF becomes unavailable. In that case,
AK7712A has DC offset of a few millivolts.
„ Zero detection function
In the case that "0" of both channels of input data repeats 8192 times, DZF becomes "H". After that, if input data
becomes not "0" then DZF becomes "L" at once.
0180-E-02
- 74 -
1997/12