AK7712A-VT Datasheet, PDF (44/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
[AK7712A-VT]
The controlling of reading/writing are executed by micro code and have functions as follows.
DLR
:
DLW
:
DRF
:
IOR
:
IORL
:
@IOR
:
@IORL :
@DADR :
@OFP
:
<List of Control Command Related External RAM>
read RAM
write RAM
RAM refresh(needed at using DRAM or Pseudo SRAM)
output RAM data to upper 16 bits of DBUS
output RAM data to lower 8 bits of DBUS
output upper 16 bits of DBUS data to data register for writing
output lower 8 bits of DBUS data to data register for writing
(at external RAM-4bit, output the middle 8 bits to data register for writing)
use upper 16bits of DBUS data for address
upper 8bits of DBUS data to pointer
„ Peak Detection
Peak detection finds upper 16 bits of DBUS data as binary. The relation of input data and transformed value which
shows the size of data is as follows. If this value is used as indirect shift of @SHR command, data can be
normalized.
input data
01**************/10**************
001*************/110*************
0001************/1110************
00001***********/11110***********
000001**********/111110**********
0000001*********/1111110*********
00000001********/11111110********
000000001*******/111111110*******
0000000001******/1111111110******
00000000001*****/11111111110*****
000000000001****/111111111110****
0000000000001***/1111111111110***
00000000000001**/11111111111110**
000000000000001*/111111111111110*
0000000000000001/1111111111111110
0000000000000000/1111111111111111
transformed value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
0180-E-02
- 44 -
1997/12