AK7712A-VT Datasheet, PDF (73/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
[AK7712A-VT]
The external conditional jump can be written at reset/run state. These timing are shown in Fig.42 and 43. At reset
state, the "L"→"H" in WRQ must be executed after 3MCK from "L"→"H" in RST. But, at run state, "L"→"H" in WRQ
can be executed at once after transferring jump condition. WRDY signal becomes "H"→"L" after transferring jump
condition, and 2 cycles after setting RST/WRQ to "H", becomes "L"→"H" at rising edge of LRCK. As similar to
above, data transferring is suppressed in the period of WRDY="L".
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Fig.42 Write Timing External Conditional Jump at Reset
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Fig.43 Write Timing of External Conditional Jump at Run time
0180-E-02
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1997/12