AK7712A-VT Datasheet, PDF (2/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
[AK7712A-VT]
Detail Features
1) Calculate Unit
•_{Multiplication:}
24-bit × 16-bit→ 40-bit(fixed-point, 2 instruction cycle time)
•_Division:
16-bit ÷ 16-bit→ 16-bit(fixed-point, 17 instruction cycle time)
•_ALU:
34-bit arithmetic operation
24-bit arithmetic logic operation
•_Shift:
1-,2-,3-,4-,6-,8-,15-bit right/left shift
AK7712A has indirect shift function.
(A shift using DBUS data can not use DBUS
•_Register:
as multiplication input.)
34-bit × 4(ACC) [for ALU]
24-bit × 8(TMP) [for DBUS connection]
•_{Double precision operation:}
24-bit(data)×31-bit(coefficient), 45 × 31, 45 × 16
2) Internal Memory
•_{Program RAM:}
384 word × 32-bit
•_{Data RAM:}
128 word × 24-bit
•_{Coefficient RAM:}
256 word × 16-bit
•_{Offset RAM:}
40 word × 16-bit (for external memory access)
•_{Microcomputer buffer: 16 word × 16-bit}
3) External Memory Access (SRAM^•Pseudo-SRAM^•DRAM)
•_{Objective memory:}
256k(32k × 8-bit),1M(128k × 8-bit) × 1 / SRAM
256k(32k × 8-bit),1M(128k × 8-bit) × 1 / Pseudo-SRAM
256k(64k × 4-bit),1M(256k × 4-bit) × 2 or × 1 / DRAM
(Half volume of 1M DRAM is used as 512k memory.)
•_{Treating bit length:}
16-bit (24-bit is available, but double time is needed for access.)
•_{The number of times to access:}
SRAM, 256k Pseudo-SRAM ; 76 at 384fs
: DRAM, 1M Pseudo-SRAM ; 64 at 384fs (32 at one DRAM)
: SRAM, 256k Pseudo-SRAM ; 51 at 256fs
: DRAM, 1M Pseudo-SRAM ; 42 at 256fs (21 at one DRAM)
•_{Memory access time:}
less than 100nsec
•_{Maximum address length:}
65535 sampling times (at 1M SRAM)
2.048sec at 32kHz, 1.486sec at 44.1kHz, 1.365sec at 48kHz
4) Input/Output Port
•_{Input: 2ch analog input: 20-bit ADC, DR=98dB (16-bit at BCLK=32fs)}
[when built-in ADC is connected.]
2ch digital input: MSB justified 20-bit (16bit at BCLK=32fs)
…_{MSB first serial input}
[when built-in ADC is isolated.]
2ch digital input: MSB justified 16- ^•24-bit / LSB justified 16-^•24-bit
…_{MSB first serial input}
•_{Output: 4ch analog output: 20-bit DAC, DR=97dB(16-bit at BCLK=32fs)}
[when built-in ADC is connected.]
4ch digital output: MSB justified 20-bit (16bit at BCLK=32fs)
…_{MSB first serial output}
[when built-in ADC is isolated.]
2ch digital output: MSB justified 16- ^•24-bit/ LSB justified 16-bit
…_{MSB first serial output}
5) Cascade connection with this LSI is possible.
6) Interface to Microcomputer:
synchronized 8-bit serial input / synchronized 24-bit serial output
7) Calculation Cycle:
max 18.432MHz(54nsec) [at 48.0kHz, 384fs, 5V]
8) Master/Slave conversion of LRCK BCLK is possible.
9) BCLK:
32fs/48fs/64fs (64fs only at master mode)
0180-E-02
-2-
1997/12