AK7712A-VT Datasheet, PDF (76/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
[AK7712A-VT]
„ Notes on Use
1) In the case that external clock is not supplied at run state
At run state(PD="H"), do not stop each external clock. XTI at master mode, and XTI,BCLK and LRCK at slave mode
are needed. If these clocks are not supplied, the circuit is overloaded and the action becomes abnormal since the
dynamic logic is used inside.
2) In the case that system clock frequency is changed
At slave mode, the inside timing must be synchronized with LRCK supplied from outside. This synchronization is
done by reset inside master counter. This reset is done only one time at LRCK"↑" after RST "↑". After that, digital
filter operates only with inside master clock, writes data to output register. In the case that synchronism breaks down
by changing each system clock frequency, the output data may become anomaly for overlap of write timing to output
register and read timing by LRCK. So, change clock with RST "L"(PDAD,PDDA="L"), and reset both built-in
ADC,DAC. But, the phase shift between LRCK and inside timing is out of the range from 1/16 to -1/16 of input
sampling cycle(1/fs), the adjustment of phase of inside timing is done synchronized with LRCK"↑"(same as reset
state).
0180-E-02
- 76 -
1997/12