AK7712A-VT Datasheet, PDF (41/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
It is explained below how the timing of previous page is go in actual program.
[AK7712A-VT]
,OP,
,,,DU1,,
,
;be able to output for DBUS and multiplier(DR) 2 steps after.
,OP,
,,, ,,
,
;
,OP,CR*DR ,,,DU1,,DRAM,
;
,OP,
,,, ,,TMP0 ,@DRAM ;write the value of TMP0 to the address made 1 step before by DU1
,OP,CR*DR ,,, ,,
,
;write the data written 1 step before by @DRAM to DR and DBUS.
,OP,
,,,DPC,,
,
;
,OP,
,,, ,,
,
;
,OP,
,,, ,,
,
;output the data of pointer changed 2 steps before by DPC.
,OP,
,,, ,,
,
;operation with changed pointer until the next DPC is executed
„ External RAM Control Unit
This unit controls the creation of write/read address, the RAM controlling signal and the receiving/transferring of 16-
bit delay data. 32k,128k×8-bit memories are used for SRAM and Pseudo SRAM, both or one of 64K and 256k ×4-bit
memories are used for DRAM. Addresses are received from OFRAM(40word × 16bit) data or inner calculation data,
i.e. DBUS data. The writing for external memory is done from small address number (00→01→02→03^……) with ring
address method.
In the case of using OFRAM, the relative address is read from OFRAM in order of execution, and the real address is
calculated. So it needs to write the address data to OFRAM in order of execution. Each external
memory access requires 5 cycles of step DSP instruction at SRAM,P-SRAM(256k), and 6 cycles at
DRAM,P-SRAM(1M). Writing of data to OFRAM is loaded from microcomputer or other unit at reset of
this LSI. At running state of LSI, if first address of changing data is appointed, 16 data can be automatically
changed at maximum in order of set address. When all data is changed, this command is automatically canceled . At
the case of using CRAM or internal calculation data(set the address by @DADR), after 2 cycles from @DADR
command execution, the execution of read/write command becomes be possible, on this time OFRAM does not
read next data. The maximum access number of times of memory are 76 for SRAM and Pseudo SRAM(256k) at
384fs, 51 at 256fs(DRAM, Pseudo SRAM(1M): 64/384fs, 42/256fs), and access time of usable memory is due to
input frequency of master clock(XTI) and sort of RAM for use, refer to switching features described in 18 - 19 page.
The timings are shown in Fig.1 for external RAM and SRAM, Fig.2, 3 for Pseudo 256k-SRAM at using auto-refresh
and static column mode read/write cycle, Fig.2 and 4 for Pseudo 1M-SRAM at using auto-refresh, read cycle and
write cycle (OE clock), Fig.5,6 for DRAM at using CAS before RAS refresh cycle and page mode read/write cycle.
<Address of Delay Data>
* Real address = OFRAM data
+ sampling frequency after RUN
= calculation data + sampling frequency after RUN
* Relation of Write/Read address
appointed address: 2000H(Write)
↑
When the appointment of writing is not exist between these address,
Delay data of 2000H(Write) is read.
↓
appointed address: 1000H(Read)
Delay time of these above = (Write address-Read address) × ( 1/fs )
(2000H-1000H) × (1/44100) = 92.9msec
0180-E-02
- 41 -
1997/12