AK7712A-VT Datasheet, PDF (17/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
[AK7712A-VT]
1) Audio Interface Timing
(AVDD=DVDD,AVB,DVB=5.0V±5%,Ta=25°C;
Master clock 16.9344MHz,XTI=384fs[fs=44.1kHz]; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Slave mode
BCLK cycle
tBLK
312.5
ns
BCLK pulse width Low
pulse width High
Time from BCLK"↓" to LRCK (note 1)
tBLKL
tBLKH
tBLR
100.0
100.0
30-tBLKH
ns
ns
30+tBLKL
ns
Delay time from LRCK to DOUT(MSB)
Delay time from BCLK"↓" to DOUT
Latch hold time of SDIN
Latch setup time of SDIN
tLRD
tBLKD
tDINH
40
tDINS
40
70
ns
70
ns
ns
ns
Master mode
BCLK cycle
Duty cycle
tBLK
64fs
ns
50
ns
BCLK pulse width Low
pulse width High
Time from BCLK"↓" to LRCK
Delay time from LRCK to DOUT(MSB)
Delay time from BCLK"↓" to DOUT
tBLKL
tBLKH
tBLR
tLRD
tBLKD
100.0
100.0
-20
ns
ns
20
ns
70
ns
70
ns
Latch hold time of SDIN
tDINH
40
ns
Latch set Up time of SDIN
tDINS
40
ns
note 1 : This standard value is provided for not to be overlapped the edge of LRCK and BCLK"↑" each other.
2) Microcomputer Interface Timing
(AVDD=DVDD,AVB,DVB=5.0V±5%,Ta=25°C;
master clock 16.9344MHz,XTI=384fs[fs=44.1kHz];CL=20pF)
Parameter
Symbol
min
typ
From CS"↓" to WRQ"↓"
tCSW
100
From RST"↓" to WRQ"↓"
From WRQ"↑" to CS"↑"
From WRQ"↑" to RST"↑"
tRSW
100
tWRC
100
tWRS
100
From WRQ"↓" to SCLK"↓"
From Last SCLK"↑" to WRQ"↑"
tWSC
100
tSCW
166(note1)
SCLK cycle
tSLK
200
SCLK pulse width Low
tSLKL
80
pulse width High
tSLKH
80
SI latch hold time
tSIH
50
SI latch set Up time
tSIS
50
From CS"↓" to
tCSHR
cancellation of SO,WRDY "Hi-z" (note2)
From CS"↑" to SO,WRDY"Hi-z" (note2)
tCSHS
From CS"↑" to DRDY"↓"
tCSDR
From SCLK"↓" to SO setup time (note2)
tSOS
note 1 : Master clock cycle × 3
note 2 : See timing chart.
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
ns
800
ns
100
ns
40
ns
0180-E-02
- 17 -
1997/12