AK7712A-VT Datasheet, PDF (72/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
[AK7712A-VT]
In case of changing the data of CRAM and OFRAM data at RUN state, execute preparation of writing data at run
state(in this case, address is unnecessary and RST is "H") by writing to buffer memory similar to Fig.11. Secondary,
set WRQ to "L" and if input of command code and address is finished then set WRQ to "H". If the preparation for
rewrite is finished inside, WRDY signal becomes "L", and rewrite command is executed from rising of LRCK. And if
rewriting is finished, WRDY becomes to "H". These timing is shown in Fig.41.
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Fig.41 Data Rewrite Timing at Run State
0180-E-02
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1997/12