AK7712A-VT Datasheet, PDF (50/87 Pages) Asahi Kasei Microsystems – Built-in 20-bit ADC/DAC Sophisticated Audio DSP

ASAHI KASEI
„ Input/Output Function
[AK7712A-VT]
DSP unit of AK7712A has 4 channels of digital input port and 6 channels of digital output port. 2 channels of input
ports (SDIN2) can be connected to internal ADC, 2 channels of output ports (SDOUT2) can be connected to
internal DAC1. And another 2 channels of output ports(SDOUT3) can be connected to internal DAC2. The command
related to these above is as follows.
INL1(DINL):
INR1(DINR):
INL2(ADCL):
INR2(ADCR):
@OTL1(@DOTL):
@OTR1(@DOTR):
@OTL2(@DAL1):
@OTR2(@DAR1):
@OTL3(@DAL2):
@OTR3(@DAR2):
<List of ADC/DAC Command>
SDIN1-Lch→DBUS (connect SDIN1 )
SDIN1-Rch→DBUS (connect SDIN1 )
SDIN2-Lch→DBUS (connect SDIN2 )
SDIN2-Rch→DBUS (connect SDIN2 )
DBUS→SDOUT1-Lch register (connect SDOUT1 )
DBUS→SDOUT1-Rch register (connect SDOUT1 )
DBUS→SDOUT2-Lch register (connect SDOUT2 )
DBUS→SDOUT2-RCh register (connect SDOUT2 )
DBUS→SDOUT3-Lch register (connect SDOUT3 )
DBUS→SDOUT3-Rch register (connect SDOUT3 )
1) Digital Serial Input
The AK7712 provides 4 channels of digital serial input unit, and each interface format is as follows. This appointment
is done at control register.
SDIN1: MSB justified 24/16-bit, LSB justified 16-bit
SDIN2: MSB justified 20/16-bit
The data which is input from SDIN1(SDIN2) is distributed to each register DINL•DINR(ADCL•ADCR) at each rising
and falling edge of LRCK, and these data are output to DBUS 1 sampling cycle after. According to each data length,
the data is supplemented by "0" to lower bit, and is output to DBUS following SRC field.
2) Digital Serial Output
The AK7712 provides 6 channels of digital serial input unit, and each interface format is mentioned below. This
appointment is done at control register.
SDOUT1: MSB justified 24/16-bit, LSB justified 16-bit
SDOUT2: MSB justified 20/16-bit
Data is loaded to register by SRC field. MSB justified interface output the data taken 1 cycle before. At the rising
edge of LRCK both data of Lch and Rch are set to parallel/serial transformation register from upper bit of DBUS. In
the case above, it can not be guaranteed that the output command of last 4 steps of execution step in program are
output by the timing mentioned below.
0180-E-02
- 50 -
1997/12