Z85C3008PEG Datasheet, PDF (73/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
65
Table 10. Z80C30 Read/Write Timing¹ (continued)
8 MHz
10 MHz
No Symbol
41 TwPCh
42 TcPC
43 TrPC
44 TfPC
Parameter
PCLK High Width
PCLK Cycle Time
PCLK Rise Time
PCLK Fall Time
Min Max Min Max
50
1000
40
1000
125 2000 100 2000
10
10
10
10
Notes:
1. Units in nanoseconds (ns) unless otherwise noted.
2. Parameter does not apply to Interrupt Acknowledge transactions.
3. Parameter applies only between transactions involving the SCC.
4. Float delay is defined as the time required for a 0.5 V change in the output with a maximum DC load and a min-
imum AC load.
5. Open-drain output, measured with open-drain test load.
6. Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of
TdAS(IEO) for the highest priority device in the daisy chain TsiEI(DSA) for the Z-SCC, and TdIElf(IEO) for each
device separating them in the daisy chain.
7. Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction.
8. Internal circuitry allows for the reset provided by the ZB to be recognized as a reset by the Z-SCC. All timing ref-
erences assume 20 V for a logic “1” and 08 V for a logic “0”.
PS011706-0511
Electrical Characteristics