Z85C3008PEG Datasheet, PDF (14/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
6
pins. Both pins are Schmitt-trigger buffered to accommodate slow rise-time signals. The
SCC detects pulses on these pins and can interrupt the CPU on both logic level transitions.
DTR/REQA, DTR/REQB
Data Terminal Ready/Request (outputs, active Low) . These outputs follow the state
programmed into the DTR bit. They can also be used as general-purpose outputs or as
Request lines for a DMA controller.
IEI
Interrupt Enable In (input, active High) . IEI is used with IEO to form an interrupt
daisy-chain when there is more than one interrupt driven device. A high IEI indicates that
no other higher priority device has an interrupt under service or is requesting an interrupt.
IEO
Interrupt Enable Out (output, active High) . IEO is High only if IEI is High and the
CPU is not servicing the SCC interrupt or the SCC is not requesting an interrupt (interrupt
Acknowledge cycle only). IEO is connected to the next lower priority device’s IEI input
and thus inhibits interrupts from lower priority devices.
INT
Interrupt Request (output, open-drain, active Low) . This signal activates when the
SCC requests an interrupt.
INTACK
Interrupt Acknowledge (input, active Low) . This signal indicates an active Interrupt
Acknowledge cycle. During this cycle, the SCC interrupt daisy chain settles. When RD is
active, the SCC places an interrupt vector on the data bus (if IEI is High). INTACK is
latched by the rising edge of PCLK.
PCLK
Clock (input) . This is the master SCC clock used to synchronize internal signals. PCLK
is a TTL level signal. PCLK is not required to have any phase relationship with the master
system clock. The maximum transmit rate is 1/4 PCLK.
PS011706-0511
Pin Descriptions